FDMF6704V datasheet(5/15 Pages) ONSEMI

Part #	FDMF6704V

Description	The Xtra Small, High Performance, High Frequency DrMOS Module with LDO

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Manufacturer	ONSEMI [ON Semiconductor]

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FDMF6704V Rev. C

Electrical Characteristics

VIN = 12 V, VDRV = 12 V, TA = 25 °C unless otherwise noted.

Parameter

Symbol

Conditions

Min

Typ

Max Units

Operating Quiescent Current

IQ

PWM = GND

2

mA

PWM = VCIN

2

Internal 5V Regulator

Input Voltage

VDRV

8

14

V

Input Current

IVDRV

8V < VIN < 14V, 1MHz

36

mA

Output voltage

VCIN

VDRV = 8V, ILoad = 5mA

4.8

5

5.2

V

Power Dissipation

PVDRV

VDRV = 12V, 1MHz

250

mW

VCIN Capacitor

CVCIN

X7R Ceramic

4.7

10

F

Line Regulation

8V < VDRV < 14V, ILoad = 5mA

20

mV

Load Regulation

VDRV = 8V, 5mA < ILoad < 100mA

75

mV

Short Circuit Current Limit

200

mA

UVLO Threshold

7.5

V

UVLO COMP Hysteresis

0.5

V

PWM Input

Sink Impedance

PWM to GND

10

k

Source Impedance

PWM to VCIN

10

k

Tri-State Rising Threshold

3.2

3.4

3.6

V

Tri-State Rising Hysteresis

100

mV

Tri-State Falling Threshold

1.2

1.4

1.6

V

Tri-State Falling Hysteresis

100

mV

Tri-State Pin Open

2.5

V

Tri-State Shut Off Time

100

ns

SMOD# and DISB# Input

High Level Input Voltage

2

V

Low Level Input Voltage

0.8

V

Input Bias Current

-2

2

A

Propagation Delay Time

PWM = GND, delay between SMOD#

or DISB# from HI to LO to GL from HI

to LO.

15

ns

High Side Driver

Rise Time

10 % to 90 %

25

ns

Fall Time

90 % to 10 %

20

ns

Deadband Time

tDTHH

GL going LO to GH going HI, 10 % to

10 %

25

ns

Propagation Delay

tPDHL

PMW going LO to GH going LO

10

ns

Low Side Driver

Rise Time

10 % to 90 %

25

ns

Fall Time

90 % to 10 %

20

ns

Deadband Time

tDTLH

VSWH going LO to GL going HI, 10

% to 10 %

20

ns

Propagation Delay

tPDLL

PWM going HI to GL going LO

10

ns

250 ns Time Out Circuit

250 ns Time Delay

Delay between GH from HI to LO and

GL from LO to HI if VSWH is high.

250

ns

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