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IDT72V36104 Datasheet(PDF) 5 Page - Integrated Device Technology |
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IDT72V36104 Datasheet(HTML) 5 Page - Integrated Device Technology |
5 / 36 page COMMERCIALTEMPERATURERANGE IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFOTM WITH BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2, 65 and 536 x 36 x 2 5 Symbol Name I/O Description FS0/SD Flag Offset Select 0/ I FS1/ SENand FS0/SD are dual-purpose inputs used for flag offset register programming. During Master Serial Data Reset, FS1/ SENandFS0/SD,togetherwith FS2,selecttheflagoffsetprogrammingmethod.Threeoffset register programming methods are available: automatically load one of five preset values (8, 16, 64, 256 or 1,024), parallel load from Port A, and serial load. FS1/ SEN FlagOffsetSelect1/ I Serial Enable, When serial load is selected for flag offset register programming, FS1/ SENis used as an enable synchronous to the LOW-to-HIGH transition of CLKA. When FS1/ SENis LOW, a rising edge on CLKA load FS2(1) Flag Offset Select 2 I the bit present on FS0/SD into the X and Y registers. The number of bit writes required to program the offset registers is 56 for the IDT72V3684, 60 for the IDT72V3694, and 64 for the IDT72V36104. The first bit write stores the Y- register (Y1) MSB and the last bit write stores the X-register (X2) LSB. MBA Port A Mailbox I A HIGH level on MBA chooses a mailbox register for a Port A read or write operation. When the A0-A35 Select outputs are active, a HIGH level on MBA selects data from the mail2 register for output and a LOW level selects FIFO2 output register data for output. MBB Port B Mailbox I A HIGH level on MBB chooses a mailbox register for a Port B read or write operation. When the B0-B35 Select outputs are active, a HIGH level on MBB selects data from the mail1 register for output and a LOW level selects FIFO1 output register data for output. MBF1 Mail1 Register O MBF1is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register. Writes to the mail1 Flag register are inhibited while MBF1 is LOW. MBF1 is set HIGH by a LOW-to-HIGH transition of CLKB when a Port B read is selected and MBB is HIGH. MBF1 is set HIGH following either a Master or Partial Reset of FIFO1. MBF2 Mail2 Register O MBF2is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register. Writes to the mail2 Flag register are inhibited while MBF2is LOW. MBF2 is set HIGH by a LOW-to-HIGH transition of CLKA when a Port A read is selected and MBA is HIGH. MBF2 is set HIGH following either a Master or Partial Reset of FIFO2. MRS1 FIFO1 Master I A LOW on this pin initializes the FIFO1 read and write pointers to the first location of memory and sets the Port Reset B output register to all zeroes. A LOW-to-HIGH transitionon MRS1selectstheprogrammingmethod(serialorparallel) and one of five programmable flag default offsets for FIFO1 and FIFO2. It also configures Port B for bus size and endian arrangement. Four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while MRS1is LOW. MRS2 FIFO2 Master I A LOW on this pin initializes the FIFO2 read and write pointers to the first location of memory and sets the Port A Reset output register to all zeroes. A LOW-to-HIGH transition on MRS2,toggledsimultaneouslywithMRS1,selectsthe programming method (serial or parallel) and one of the programmable flag default offsets for FIFO2. Four LOW-to- HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while MRS2 is LOW. PRS1/ PartialReset/ I This pin is muxed for both Partial Reset and Retransmit operations, it is used in conjunction with the RTM pin. RT1 RetransmitFIFO1 If RTM is in a LOW condition, a LOW on this pin performs a Partial Reset on FIFO1 and initializes the FIFO1 read andwritepointerstothefirstlocationofmemoryandsetsthePortBoutputregistertoallzeroes.DuringPartialReset, the currently selected bus size, endian arrangement, programming method (serial or parallel), and programmable flag settings are all retained. If RTM is HIGH, a LOW on this pin performs a Retransmit and initializes the FIFO1 read pointer only to the first memory location. PRS2/ PartialReset/ I This pin is muxed for both Partial Reset and Retransmit operations, it is used in conjunction with the RTM pin. RT2 RetransmitFIFO2 If RTMis in a LOW condition, a LOW on this pin performs a Partial Reset on FIFO2 and initializes the FIFO2 read and write selected bus size, endian arrangement, programming method (serial or parallel), and programmable flag settingsareallretained.IfRTMisHIGH,aLOWonthispinperformsaRetransmitandinitializestheFIFO2readpointer only to the first memory location. RTM RetransmitMode I This pin is used in conjunction with the RT1 and RT2 pins. When RTM is HIGH a Retransmit is performed on FIFO1 or FIFO2 respectively. SIZE(1) Bus Size Select I A HIGH on this pin when BM is HIGH selects byte bus (9-bit) size on Port B. A LOW on this pin when BM is HIGH selects word (18-bit) bus size. SIZE works with BM and BE to select the bus size and endian arrangement for Port B. The level of SIZE must be static throughout device operation W/ RA Port-AWrite/ I A HIGH selects a write operation and a LOW selects a read operation on Port A for a LOW-to-HIGH Read Select transition of CLKA. The A0-A35 outputs are in the HIGH impedance state when W/ RAis HIGH. W/RB Port-BWrite/ I A LOW selects a write operation and a HIGH selects a read operation on Port B for a LOW-to-HIGH Read Select transition of CLKB. The B0-B35 outputs are in the HIGH impedance state when W/RB is LOW. PIN DESCRIPTIONS (CONTINUED) NOTE: 1. FS2, BM and SIZE inputs are not TTL compatible. These inputs should be tied to GND or VCC. |
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