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IDT5V9351 Datasheet(PDF) 6 Page - Integrated Device Technology

Part No. IDT5V9351
Description  LOW VOLTAGE PLL CLOCK DRIVER
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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IDT5V9351 Datasheet(HTML) 6 Page - Integrated Device Technology

 
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INDUSTRIALTEMPERATURERANGE
6
IDT5V9351
LOWVOLTAGEPLLCLOCKDRIVER
DC ELECTRICAL CHARACTERISTICS
TA = -40°C to +85°C, VCC = 2.5V ± 5%
Symbol
Parameter
Test Conditions
Min.
Typ.
Max
Unit
VIH
Input HIGH Voltage
LVCMOS Inputs
1.7
VCC + 0.3
V
VIL
InputLOWVoltage
LVCMOS Inputs
0.7
V
VPP
Peak-to-PeakInputVoltage
PECL_CLK
250
mV
VCMR
Common Mode(1)
PECL_CLK
1
VCC - 0.6
V
VOH
Output HIGH Voltage(2)
IOH = -15mA
1.8
V
VOL
OutputLOWVoltage(2)
IOL = 15mA
0.6
V
IIN
InputCurrent
±150
µA
CIN
InputCapacitance
4
pF
ZOUT
OutputImpedance
17 - 20
CPD
PowerDissipationCapacitance
10
pF
ICC
Maximum Quiescent Supply Current
All VCC Pins
1
mA
ICCPLL
Maximum PLL Supply Current
VCCA Only
3
5
mA
NOTES:
1. VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the HIGH input is within the VCMR range and the input swing
lies within the VPP specification.
2. The IDT5V9351 outputs can drive series or paralell terminated 50
Ω (or 50Ω to VCC/2) transmission lines on the incident edge.
PLL INPUT REFERENCE CHARACTERISTICS
VCC = 2.5V ± 5%, TA = -40°C to +85°C
Symbol
Parameter
Min.
Max
Unit
tR, tF
TCLK Input Rise/Fall Levels, 0.7V to 1.7V
1
ns
÷ 2feedback
100
200
fREF
ReferenceInputFrequency(1)
÷ 4feedback
50
100
MHz
÷ 8feedback
25
50
fREFDC
Reference Input Duty Cycle
25
75
%
NOTE:
1. Maximum and minimum input reference is limited by the VCO lock range and the feedback divider for the TCLK or PECL_CLK inputs.


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