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IDT5V9351 Datasheet(PDF) 3 Page - Integrated Device Technology

Part No. IDT5V9351
Description  LOW VOLTAGE PLL CLOCK DRIVER
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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IDT5V9351 Datasheet(HTML) 3 Page - Integrated Device Technology

 
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INDUSTRIALTEMPERATURERANGE
IDT5V9351
LOWVOLTAGEPLLCLOCKDRIVER
3
Terminal
Name
No.
Type
Description
PECL-CLK
8, 9
I
Differentialclockreference,LOWvoltagepositiveECLinput
PECL-CLK
TCLK
30
I
Single-endedreferenceclocksignalortestclock
FBIN
2
I
Feedbacksignalinput
REF_SEL
32
I
Referenceclockinput
fSEL(D:A)
3, 4, 5, 6
I
Frequencycontrolpin
OE
10
I
Outputenable/disable
QA
28
O
Bank A clock output
QB
26
O
Bank B clock output
QC(1:0)
22,24
O
Bank C clock output
QD(4:0)
12, 14, 16,
O
Bank D clock output
18,20
VCCA
1
PWR
Positive power supply for PLL
VCC
11, 15, 19,
PWR
Positive power supply for I/O and core
23,27
GND
7, 13, 17, 21,
Ground
Negative power supply
25,29
PLL_EN
31
I
PLL enable input. When set HIGH, PLL is enabled. When set LOW, PLL is disabled.
PIN DESCRIPTION
FUNCTIONALITY
Control
Default
0
1
REF_SEL
0
Selects PECL_CLK as reference clock
Selects TCLK as reference clock
PLL_EN
1
Test modewithPLLDisabled
PLLEnabled
OE
0
Outputsenabled
Outputsdisabled
FSELA
0
QA = VCO
÷ 2QA = VCO ÷ 4
FSELB
0
QB = VCO
÷ 4QB = VCO ÷ 8
FSELC
0
QC = VCO
÷ 4QC = VCO ÷ 8
FSELD
0
QD = VCO
÷ 4QD = VCO ÷ 8
NOTE:
1. Output frequency relationship with respect to input reference frequency CLK. QC1 is connected to FBIN.


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