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IDT72T1895L10BBI Datasheet(PDF) 5 Page - Integrated Device Technology |
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IDT72T1895L10BBI Datasheet(HTML) 5 Page - Integrated Device Technology |
5 / 55 page 5 COMMERCIALANDINDUSTRIAL TEMPERATURERANGES IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/ 8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9 The device can be configured with different input and output bus widths as shown in Table 1. A Big-Endian/Little-Endian data word format is provided. This function is useful when data is written into the FIFO in long word format (x18) and read out of the FIFO in small word (x9) format. If Big-Endian mode is selected, then themostsignificantbyte(word)ofthelongwordwrittenintotheFIFOwillberead outoftheFIFOfirst,followedbytheleastsignificantbyte.IfLittle-Endianformat is selected, then the least significant byte of the long word written into the FIFO will be read out first, followed by the most significant byte. The mode desired is configured during master reset by the state of the Big-Endian ( BE) pin. The Interspersed/Non-Interspersed Parity (IP) bit function allows the user to select the parity bit in the word loaded into the parallel port (D0-Dn) when programming the flag offsets. If Interspersed Parity mode is selected, then the FIFOwillassumethattheparitybitislocatedinbitpositionsD8duringtheparallel programming of the flag offsets. If Non-Interspersed Parity mode is selected, then D8 is assumed to be a valid bit and D16 and D17 are ignored. IP mode is selected during Master Reset by the state of the IP input pin. This mode is relevant only when the input width is set to x18 mode. If, at any time, the FIFO is not actively performing an operation, the chip will automatically power down. Once in the power down state, the standby supply currentconsumptionisminimized. Initiatinganyoperation(byactivatingcontrol inputs) will immediately take the device out of the power down state. Both an Asynchronous Output Enable pin ( OE) and Synchronous Read Chip Select pin ( RCS)areprovidedontheFIFO.TheSynchronousReadChip SelectissynchronizedtotheRCLK.Boththeoutputenableandreadchipselect control the output buffer of the FIFO, causing the buffer to be either HIGH impedance or LOW impedance. A JTAG test port is provided, here the FIFO has fully functional Boundary Scan feature, compliant with IEEE 1449.1 Standard Test Access Port and Boundary Scan Architecture. The TeraSync FIFO has the capability of operating its ports (write and/or read) in either LVTTL or HSTL mode, each ports selection independent of the other. The write port selection is made via WHSTL and the read port selection via RHSTL. An additional input SHSTL is also provided, this allows the user to select HSTL operation for other pins on the device (not associated with the write or read ports). The IDT72T1845/72T1855/72T1865/72T1875/72T1885/72T1895/ 72T18105/72T18115/72T18125 are fabricated using IDT’s high speed sub- micron CMOS technology. |
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