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IDT72T1855L10BB Datasheet(PDF) 9 Page - Integrated Device Technology |
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IDT72T1855L10BB Datasheet(HTML) 9 Page - Integrated Device Technology |
9 / 55 page 9 COMMERCIALANDINDUSTRIAL TEMPERATURERANGES IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/ 8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9 PIN DESCRIPTION (CONTINUED) NOTES: 1. Inputs should not change state after Master Reset. 2. These pins are for the JTAG port. Please refer to pages 29-32 and Figures 6-8. Symbol Name I/O TYPE Description WHSTL(1) Write Port HSTL LVTTL This pin is used to select HSTL or 2.5V LVTTL inputs for the FIFO. If HSTL inputs are required, this input must Select INPUT be tied HIGH. Otherwise it should be tied LOW. VCC +2.5V Supply I These are VCC supply inputs and must be connected to the 2.5V supply rail. GND Ground Pin I These are Ground pins and must be connected to the GND rail. Vref Reference I This is a Voltage Reference input and must be connected to a voltage level determined from the table, Voltage “Recommended DC Operating Conditions”. This provides the reference voltage when using HSTL class inputs. If HSTL class inputs are not being used, this pin should be tied LOW. VDDQ O/P Rail Voltage I This pin should be tied to the desired voltage rail for providing power to the output drivers. |
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