6

A falling transition on PWM indicates the turn-off of the upper

MOSFET and the turn-on of the lower MOSFET. A short

shoot-through circuitry determines the lower gate delay time

monitored, and the lower gate is allowed to rise, after the

upper MOSFET gate-to-source voltage drops below 1V. The

MOSFET.

This driver is optimized for converters with large step down

ratio, such as those used in a mobile-computer core voltage

regulator. The lower MOSFET is usually sized much

larger.Timing Diagram

This driver is optimized for converters with large step down

compared to the upper MOSFET because the lower

MOSFET conducts for a much longer time in a switching

period. The lower gate driver is therefore sized much larger

to meet this application requirement. The 0.4

Ω on-resistance

and 4A sink current capability enable the lower gate driver to

absorb the current injected to the lower gate through the

drain-to-gate capacitor of the lower MOSFET and prevent a

shoot through caused by the high dv/dt of the phase node.

Three-State PWM Input

A unique feature of the ISL6209 and other Intersil drivers is

the addition of a shutdown window to the PWM input. If the

PWM signal enters and remains within the shutdown window

for a set holdoff time, the output drivers are disabled and

both MOSFET gates are pulled and held low. The shutdown

state is removed when the PWM signal moves outside the

shutdown window. Otherwise, the PWM rising and falling

thresholds outlined in the ELECTRICAL SPECIFICATIONS

determine when the lower and upper gates are enabled.

During start-up, PWM should be in the three-state position

Shoot-Through Protection

The ISL6209 driver delivers shoot-through protection by

incorporating gate threshold monitoring and programmable

dead-time to prevent upper and lower MOSFETs from

conducting simultaneously, thereby shorting the input supply

to ground. Gate threshold monitoring ensures that one gate

is OFF before the other is allowed to turn ON.

During turn-off of the lower MOSFET, the LGATE voltage is

monitored until it reaches a 1V threshold, at which time the

UGATE is released to rise. Internal circuitry monitors the

upper MOSFET gate-to-source voltage during UGATE

turn-off. Once the upper MOSFET gate-to-source voltage

has dropped below a threshold of 1V, the LGATE is allowed

to rise.

In addition to gate threshold monitoring, a programmable

delay between MOSFET switching can be accomplished by

placing a resistor from the DELAY pin to ground. This delay

allows for maximum design flexibility over MOSFET

selection. The delay can be programmed from 5ns to 50ns. If

not desired, the DELAY pin must be tied to VCC to disable

the delay circuitry. Gate threshold monitoring is not affected

by the addition or removal of the additional dead-time. Refer

to Figure 4 and Figure 5 for more detail.

PWM

UGATE

LGATE

1V

1V

FIGURE 3. TIMING DIAGRAM

ISL6209