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IDT7009L15PF Datasheet(PDF) 1 Page - Integrated Device Technology |
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IDT7009L15PF Datasheet(HTML) 1 Page - Integrated Device Technology |
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1 / 17 page  1 ©2000 Integrated Device Technology, Inc. JANUARY 2001 DSC-4839/2 I/O Control Address Decoder 128Kx8 MEMORY ARRAY 7009 ARBITRATION INTERRUPT SEMAPHORE LOGIC CE0L OEL R/ W L A16L A0L I/O0-7L SEML INTL (2) BUSYL (1,2) R/ WL CE0L OEL I/O Control Address Decoder OER R/ WR CE0R A16R A0R I/O0-7R SEMR INTR (2) R BUSY (1,2) M/ S (1) CE1L R/ WR CE0R OER CE1R 4839 drw 01 1L CE 1R CE 17 17 Functional Block Diagram x M/ S = VIH for BUSY output flag on Master, M/ S = VIL for BUSY input on Slave x Interrupt Flag x On-chip port arbitration logic x Full on-chip hardware support of semaphore signaling between ports x Fully asynchronous operation from either port x TTL-compatible, single 5V (±10%) power supply x Available in a 100-pin TQFP x Industrial temperature range (–40°C to +85°C) is available for selected speeds Features x True Dual-Ported memory cells which allow simultaneous reads of the same memory location x High-speed access – Commercial: 15/20ns (max.) x Low-power operation – IDT7009L Active: 1W (typ.) Standby: 1mW (typ.) x Dual chip enables allow for depth expansion without external logic x IDT7009 easily expands data bus width to 16 bits or more using the Master/Slave select when cascading more than one device HIGH-SPEED 128K x 8 DUAL-PORT STATIC RAM IDT7009L NOTES: 1. BUSY is an input as a Slave (M/S = VIL) and an output when it is a Master (M/S = VIH). 2. BUSY and INT are non-tri-state totem-pole outputs (push-pull). |
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