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DP83815DVNG Datasheet(PDF) 10 Page - National Semiconductor (TI) |
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DP83815DVNG Datasheet(HTML) 10 Page - National Semiconductor (TI) |
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10 / 108 page  10 www.national.com 2.0 Pin Description (Continued) Note: DP83815 supports FM93C46 for the EEPROM device. Clock Interface Symbol LQFP Pin No(s) LBGA Pin No(s) Dir Description X1 17 D8 I Crystal/Oscillator Input: This pin is the primary clock reference input for the DP83815 and must be connected to a 25 MHz 0.005% (50ppm) clock source. The DP83815 device supports either an external crystal resonator connected across pins X1 and X2, or an external CMOS-level oscillator source connected to pin X1 only. X2 18 C7 O Crystal Output: This pin is used in conjunction with the X1 pin to connect to an external 25 MHz crystal resonator device. This pin must be left unconnected if an external CMOS oscillator clock source is utilized. For more information see the definition for pin X1. LED Interface Symbol LQFP Pin No(s) LBGA Pin No(s) Dir Description LEDACTN/MA0 142 C14 O TX/RX Activity: This pin is an output indicating transmit/receive activity. This pin is driven low to indicate active transmission or reception, and can be used to drive a low current LED (<6 mA). The activity event is stretched to a min duration of approximately 50 ms. LED100N/MA2 144 C13 O 100 Mb/s Link: This pin is an output indicating the 100 Mb/s Link status. This pin is driven low to indicate Good Link status for 100 Mb/s operation, and can be used to drive a low current LED (<6 mA). LED10N/MA1 143 C12 O 10 Mb/s Link: This pin is an output indicating the 10 Mb/s Link status. This pin is driven low to indicate Good Link status for 10 Mb/s operation, and can be used to drive a low current LED (<6 mA). Serial EEPROM Interface Symbol LQFP Pin No(s) LBGA Pin No(s) Dir Description EESEL 128 G14 O EEPROM Chip Select: This signal is used to enable an external EEPROM device. EECLK/MA4 2 A12 O EEPROM Clock: During an EEPROM access (EESEL asserted), this pin is an output used to drive the serial clock to an external EEPROM device. EEDI/MA3 1 B12 O EEPROM Data In: During an EEPROM access (EESEL asserted), this pin is an output used to drive opcode, address, and data to an external serial EEPROM device. EEDO/MD4 138 E11 I EEPROM Data Out: During an EEPROM access (EESEL asserted), this pin is an input used to retrieve EEPROM serial read data. This pin has an internal weak pull up. MD1/CFGDISN 133 F13 I/O Configuration Disable: When pulled low at power-on time, disables load of configuration data from the EEPROM. Use 1 K Ω to ground to disable configuration load. |
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