PRELIMINARY
CYD04S72V
CYD09S72V
CYD18S72V
Document #: 38-06069 Rev. *D
Page 5 of 26
Master Reset
The FLEx72 family devices undergo a complete reset by
taking the MRST input LOW. MRST input can switch
asynchronously to the clocks. MRST initializes the internal
burst counters to zero, and the counter mask registers to all
ones (completely unmasked). MRST also forces the mailbox
interrupt (INT) flags and the Counter Interrupt (CNTINT) flags
HIGH. MRST must be performed on the FLEx72 family
devices after power-up.
Mailbox Interrupts
The upper two memory locations may be used for message
passing and permit communications between ports. Table 2
shows the interrupt operation for both ports using 18Mbit
device as an example. The highest memory location, 3FFFF
is the mailbox for the right port and 3FFFE is the mailbox for
the left port. Table 2.shows that in order to set the INTR flag, a
write operation by the left port to address 3FFFF will assert
INTR LOW. At least one byte has to be active for a write to
generate an interrupt. A valid Read of the 3FFFF location by
the right port will reset INTR HIGH. At least one byte has to be
active in order for a read to reset the interrupt. When one port
writes to the other port’s mailbox, the INT of the port that the
mailbox belongs to is asserted LOW.
The INT is reset when the owner (port) of the mailbox reads
the contents of the mailbox. The interrupt flag is set in
a flow-thru mode (i.e., it follows the clock edge of the writing
port). Also, the flag is reset in a flow-thru mode (i.e., it follows
the clock edge of the reading port).
Each port can read the other port’s mailbox without resetting
the interrupt. And each port can write to its own mailbox
without setting the interrupt. If an application does not require
message passing, INT pins should be left open.
TDI
JTAG Test Data Input. Data on the TDI input will be shifted serially into selected
registers.
TCK
JTAG Test Clock Input.
TDO
JTAG Test Data Output. TDO transitions occur on the falling edge of TCK.
TDO is normally three-stated except when captured data is shifted out of the
JTAG TAP.
VSS
Ground Inputs.
VCORE
Core Power Supply.
VTTL
LVTTL Power Supply.
Pin Definitions (continued)
Left Port
Right Port
Description
Table 2. Interrupt Operation Example [1, 11, 12, 13]
Function
Left Port
Right Port
R/WL
CEL
A0L–17L
INTL
R/WR
CER
A0R–17R
INTR
Set Right INTR Flag
L
L
3FFFF
X
XXX
L
Reset Right INTR Flag
XX
XX
H
L
3FFFF
H
Set Left INTL Flag
X
X
X
LLL
3FFFE
X
Reset Left INTL Flag
H
L
3FFFE
H
XXX
X
Note:
11. CE is internal signal. CE = LOW if CE0 = LOW and CE1 = HIGH. For a single Read operation, CE only needs to be asserted once at the rising edge of
the CLK and can be deasserted after that. Data will be out after the following CLK edge and will be three-stated after the next CLK edge.
12. OE is “Don’t Care” for mailbox operation.
13. At least one of BE0 or BE7 must be LOW.
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