PRELIMINARY
CY9C6264
Document#: 38-15003 Rev. *D
Page 2 of 12
Overview
The CY9C6264 is a byte-wide MRAM memory. The memory
array is logically organized as 8,192 × 8 and is accessed using
an industry standard parallel asynchronous SRAM-like
interface. The CY9C6264 is inherently nonvolatile and offers
write protect during sudden power loss. Functional operation
of the MRAM is otherwise similar to SRAM-type devices.
Memory Architecture
Users access 8,192 memory locations each with eight data
bits through a parallel interface. Internally, the memory array
is organized into 8 blocks of 128 rows x 64 columns each.
The access and cycle time are the same for Read and Write
memory operations. Unlike an EEPROM or Flash, it is not
necessary to poll the device for a ready condition since writes
occur at bus speed.
Memory Operation
The CY9C6264 is designed to operate in a manner similar to
other bytewide memory products. For users familiar with
BBSRAM, the MRAM performance is superior. For users
familiar with EEPROM, Flash, and FeRAM, the obvious differ-
ences result from higher write performance of MRAM
technology and much higher write endurance.
All memory array bits are set to logic “1” at the time of
shipment.
Read Operation
A read cycle begins whenever WE (Write Enable) is inactive
(HIGH) and CE1 (Chip Enable) and OE (Output Enable) are
active LOW while CE2 is active HIGH. The unique address
specified by the 13 address inputs (A0–A12) defines which of
the 8,192 bytes of data is to be accessed. Valid data will be
available at the eight output pins within tAA (access time) after
the last address input is stable, providing that CE1 or CE2 and
OE access times are also satisfied. If CE1 or CE2 and OE
access times are not satisfied, the data access must be
measured from the later-occurring signal (CE1, CE2 or OE)
and the limiting parameter is either tACE1 for CE1, tACE2 for
CE2, or tDOE for the OE rather than address access.
Write Cycle
The CY9C6264 initiates a Write cycle whenever the WE and
CE1 signals are active (LOW) or WE is LOW and CE2 is HIGH,
after address inputs are stable. The later occurring falling edge
of CE1 (rising in case of CE2) or WE will determine the start of
the Write cycle. The Write cycle is terminated by the earlier
rising edge of CE1 (falling edge in case of CE2) or WE. All
address inputs must be kept valid throughout the Write cycle.
The OE control signal should be kept inactive (HIGH) during
Write cycles to avoid bus contention. However, if the output
drivers are enabled (CE1 or CE2 and OE active), WE will
disable the outputs in tHZWE from the WE falling edge.
Unlike other nonvolatile memory technologies, there is no
Write delay with MRAM. The entire memory operation occurs
in a single bus cycle. Therefore, any operation including Read
or Write can occur immediately following a Write. Data Polling,
a technique used with EEPROMs to determine if the Write is
complete, is unnecessary. Page Write, a technique used to
enhance EEPROM Write performance, is also unnecessary
because of inherently fast Write cycle time for MRAM. The
total write time for the entire array is 0.575 ms.
Write Inhibit and Data Retention Mode
This feature protects against the inadvertent Write. The
CY9C6264 provides full functional capability for VCC greater
than 4.5V and Write-protects the device below 4.0V. Data is
maintained in the absence of VCC. During the power-up,
normal operation can resume 20
µs after VPFD is reached.
Refer to page 8 for details.
Sudden Power Loss—“Brown out”
The nonvolatile RAM constantly monitors VCC. Should the
supply voltage decay below the operating range, the
CY9C6264 automatically write-protects itself, all inputs
become “don’t care,” and all outputs become high impedance.
Refer to page 8 for details.
Silicon Signature/Device ID
An extra 64 bytes of MRAM are available to the user for Device
ID. By raising A7 to VCC + 2.0V and by using address locations
00 (Hex) to 3F (Hex) on address pins A6, A5, A4, A12, A11, and
A10 (MSB to LSB) respectively, the additional bytes may be
accessed in the same manner as the regular memory array
with 140ns read access time and 140ns write cycle time.
Writing the extra bytes of MRAM requires a longer address
setup to write start of 70 ns vs. the normal operating specifi-
cation of 0ns. Dropping A7 from input high (VCC + 2.0V) to <
VCC + 0.5V max. returns the device to normal operation after
140-ns delay.
All User Space bits are set to logic “1” at the time of shipment.
Magnetic Shielding
CY9C6264 is protected from external magnetic fields through
the application of a “magnetic shield” that covers the entire
memory array.
Applications
Battery-backed SRAM (BBSRAM) Replacement
CY9C6264 is designed to replace (plug and play) existing
BBSRAM while eliminating the need for battery and VCC
monitor IC, reducing cost and board space and improving
system reliability.
The cost associated with multiple components, assemblies,
and manufacturing overhead associated with battery-backed
SRAM is eliminated by using monolithic MRAM. CY9C6264
eliminates multiple assemblies, connectors, modules, field
maintenance, and environmental issues common with BB
SRAM. MRAM is a true nonvolatile RAM with high perfor-
mance, high endurance, and data retention.
Battery-backed SRAMs are forced to monitor VCC in order to
switch to the backup battery. Users that are modifying existing
designs to use MRAM in place of BBSRAM, can eliminate the
VCC controller IC along with the battery. MRAM performs this
function on-chip.
Address (MSB to LSB)
A6 A5 A4 A12 A11 A10
Description
ID
00h
Manufacturer ID
34h
01h
Device ID
41h
02h–3Fh
User Space
62 bytes
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