32K x 8 Static RAM
CY7C199C
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
, CA 95134
•
408-943-2600
Document #: 38-05408 Rev. *A
Revised September 11, 2003
Features
• Fast access time: 12 ns, 15 ns, 20 ns, and 25 ns
• Wide voltage range: 5.0V ± 10% (4.5V to 5.5V)
• CMOS for optimum speed/power
• TTL–compatible Inputs and Outputs
• Available in 28 DIP, 28 SOJ, and 28 TSOP I.
• 2.0V Data Retention
• Low CMOS standby power
• Automated Power–down when deselected
General Description1
The CY7C199C is a high–performance CMOS Asynchronous
SRAM organized as 32K by 8 bits that supports an
asynchronous memory interface. The device features an
automatic power–down feature that significantly reduces
power consumption when deselected.
See the Truth Table in this datasheet for a complete
description of read and write modes.
The CY7C199C is available in 28 DIP, 28 SOJ, and 28 TSOP
I package(s).
Product Portfolio
Notes:
1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
12 ns
15 ns
20 ns
25 ns
Unit
Maximum Access Time
12
15
20
25
ns
Maximum Operating Current
85
80
75
75
mA
Maximum CMOS Standby Current
(low power)
500
500
500
500
uA
RAM Array
Column Decoder
Input Buffer
A
X
Power
Down
Circuit
I/Ox
OE
WE
CE
X
Logic Block Diagram
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