LMX2525LQ1321 datasheet(11/17 Pages) NSC

Part #	LMX2525LQ1321

Description	PLLatinum Dual Frequency Synthesizer System with Integrated VCOs

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Manufacturer	NSC [National Semiconductor (TI)]

Direct Link	http://www.national.com

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Functional Description (Continued)

LOCKING MODES

Two frequency-locking modes are provided: a Normal mode

and a High Speed mode for faster lock times. The HS bit in

register R0 controls the locking mode.

TABLE 5. Locking Modes

HS Bit

Mode

0

Normal mode

1

High Speed mode

MICROWIRE INTERFACE

The programmable register set is accessed via the

MICROWIRE serial interface. The interface is comprised of

three signal pins: CLK, DATA, and LE (Latch Enable). Serial

data is clocked into the 24-bit shift register on the rising edge

of the clock. The last bits decode the internal control register

address. When the latch enable (LE) transitions from LOW

to HIGH, data stored in the shift registers is loaded into the

corresponding control register. The data is loaded MSB first.

20068909

FIGURE 3. Lock Detect Flow Diagram

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