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IDT77105 Datasheet(PDF) 5 Page - Integrated Device Technology

Part # IDT77105
Description  PHY (TC-PMD) for 25.6 Mbps ATM Networks
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT77105 Datasheet(HTML) 5 Page - Integrated Device Technology

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September 11, 2000
IDT77105
22
RxSOC
O
UTOPIA bus
Receive Start of Cell signal.
23
RxEmpty/RxClav
O
UTOPIA bus
Receive Empty (active low; byte mode) or Receive Cell Available (active high; cell mode).
24
RxRef
O
UTOPIA bus
Receive Reference signal (active low). This pin is driven in response to a received X_8 command byte.
Assertion duration is programmable to 1,2,4 or 8 clocks, as set via register 0x03, bits 3,4.
25
VCC
Power plane
26
RxData0
O
UTOPIA bus
Receive data bit 0.
27
RxData1
O
UTOPIA bus
Receive data bit 1.
28
RxData2
O
UTOPIA bus
Receive data bit 2.
29
RxData3
O
UTOPIA bus
Receive data bit 3.
30
RxData4
O
UTOPIA bus
Receive data bit 4.
31
RxData5
O
UTOPIA bus
Receive data bit 5.
32
GND
Ground plane
33
RxData6
O
UTOPIA bus
Receive data bit 6.
34
RxData7
O
UTOPIA bus
Receive data bit 7.
35
RxParity
O
UTOPIA bus
Parity bit for RxData[7:0].
36
RxClk
I
UTOPIA bus
Receive data path synchronization clock.
37
RxEnb
I
UTOPIA bus
Receive Enable signal (active low).
38
TxFull/TxCLAV
O
UTOPIA bus
Transmit Full (active low; byte mode) or Transmit Cell Available (active high; cell mode).
39
TxSOC
I
UTOPIA bus
Transmit Start of Cell signal.
40
TxEnb
I
UTOPIA bus
Transmit Enable signal (active low).
41
TxClk
I
UTOPIA bus
Transmit data path synchronization clock.
42
TxParity
I
UTOPIA bus
Parity bit for TxData[7:0]. If unused, this pin must be tied high or low.
43
TxData7
I
UTOPIA bus
Transmit data bit 7.
44
TxData6
I
UTOPIA bus
Transmit data bit 6.
45
TxData5
I
UTOPIA bus
Transmit data bit 5.
46
TxData4
I
UTOPIA bus
Transmit data bit 4.
47
TxData3
I
UTOPIA bus
Transmit data bit 3.
48
TxData2
I
UTOPIA bus
Transmit data bit 2.
49
TxData1
I
UTOPIA bus
Transmit data bit 1.
50
TxData0
I
UTOPIA bus
Transmit data bit 0.
51
TxRef
I
UTOPIA bus
Transmit Reference signal input (active low). Assertion (falling edge) of this pin stimulates insertion of com-
mand byte X_8 into the transmit data stream.
52
Reset
I
control
Reset signal (active low).
53
INT
O
control
Interrupt signal (active low). Always driven.
54
AD7
I/O
Utility bus
Address/Data bit 7. Not used for addressing.
55
AD6
I/O
Utility bus
Address/Data bit 6. Not used for addressing.
56
VCC
Power plane
57
AD5
I/O
Utility bus
Address/Data bit 5. Not used for addressing.
58
AD4
I/O
Utility bus
Address/Data bit 4. Not used for addressing.
59
AD3
I/O
Utility bus
Address/Data bit 3. Not used for addressing.
60
AD2
I/O
Utility bus
Address/Data bit 2.
61
AD1
I/O
Utility bus
Address/Data bit 1.
62
AD0
I/O
Utility bus
Address/Data bit 0.
63
GND
Ground plane
64
CS
I
Utility bus
Utility Bus Chip select (active low).
Pin
Name
I/O Interfaces to
Description
Table 1 Pin Description (Part 2 of 2)


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