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IDT72V7326 Datasheet(PDF) 5 Page - Integrated Device Technology

Part No. IDT72V7326
Description  3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH 16,384 X 16,384
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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IDT72V7326 Datasheet(HTML) 5 Page - Integrated Device Technology

 
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INDUSTRIAL TEMPERATURERANGE
IDT72V73260 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 16,384 x 16,384
DESCRIPTION (CONTINUED)
The IDT72V73260 is capable of switching up to 16,384 x 16,384 channels
without blocking. Designed to switch 64 Kbit/s PCM or N x 64 Kbit/s data, the
devicemaintainsframeintegrityindataapplicationsandminimizesthroughput
delay for voice applications on a per-channel basis.
The 32 serial input streams (RX) of the IDT72V73260 are run at 32.768Mb/s
allowing 512 channels per 125
µsframe.Thedataratesontheoutputstreams
(TX) are identical to those on the input streams (RX).
Withtwomainoperatingmodes,ProcessorModeandConnectionMode,the
IDT72V73260 can easily switch data from incoming serial streams (Data
Memory) or from the controlling microprocessor via Connection Memory. As
controlandstatusinformationiscriticalindatatransmission,theProcessorMode
isespeciallyusefulwhentherearemultipledevicessharingtheinputandoutput
streams.
With data coming from multiple sources and through different paths, data
enteringthedeviceisoftendelayed.Tohandlethisproblem,theIDT72V73260
hasaFrameEvaluationfeaturetoallowindividualstreamstobeoffsetfromthe
frame pulse in half clock-cycle intervals up to +7.5 clock cycles.
The IDT72V73260 also provides a JTAG test access port, memory block
programming,asimplemicroprocessorinterfaceandautomaticST-BUS®/GCI
sensing to shorten setup time, aid in debugging and ease use of the device
withoutsacrificingcapabilities.
FUNCTIONAL DESCRIPTION
DATA AND CONNECTION MEMORY
All data that comes in through the RX inputs go through a serial-to-parallel
conversion before being stored into internal Data Memory. The 8 KHz frame
pulse (F32i) is used to mark the 125
µsframeboundariesandtosequentially
address the input channels in Data Memory.
DataoutputontheTXstreamsmaycomefromeithertheserialinputstreams
(Data Memory) or from the microprocessor (Connection Memory). In the case
thatRXinputdataistobeoutput,theaddressesinConnectionMemoryareused
to specify a stream and channel of the input. The Connection Memory is setup
in such a way that each location corresponds to an output channel for each
particularstream.Inthatway,morethanonechannelcanoutputthesamedata.
InProcessorMode,themicroprocessorwritesdatatotheConnectionMemory
locationscorrespondingtothestreamandchannelthatistobeoutput.Thelower
half(8leastsignificantbits)oftheConnectionMemoryisoutputeveryframeuntil
the microprocessor changes the data or mode of the channel. By using this
Processor Mode capability, the microprocessor can access input and output
time-slots on a per-channel basis.
The two most significant bits of the Connection Memory are used to control
per-channelmodeoftheoutputstreams.Specifically,theMOD1-0bitsareused
to select Processor Mode, Constant or Variable delay Mode, and the high-
impedancestateofoutputdrivers.IftheMOD1-0bitsaresetto1-1accordingly,
only that particular output channel (8 bits) will be in the high-impedance state.
If however, the ODE input pin is LOW and the Output Standby Bit in the Control
Register is LOW, all of the outputs will be in a high-impedance state even if a
particular channel in Connection Memory has enabled the output for that
channel.Inotherwords,theODEpinandOutputStandBycontrolbitaremaster
output enables for the device (See Table 3).
SERIAL DATA INTERFACE TIMING
Fora32.768Mb/sserialdatarate,themasterclockfrequencywillberunning
at 32.768 MHz resulting in a single-bit per clock. The IDT72V73260 provides
two different interface timing modes, ST-BUS® or GCI.
The IDT72V73260 automatically detects the presence of an input frame
pulse and identifies it as either ST-BUS® or GCI. In ST-BUS® Mode, data is
clockedoutonthefallingedgeandisclockedinonthesubsequentrising-edge.
See Figure 14 for timing. In GCI Mode, data is clocked out on the rising edge
and is clocked in on the subsequent falling edge. See Figure 15 for timing.
INPUT FRAME OFFSET SELECTION
Input frame offset selection allows the channel alignment of individual input
streamstobeoffsetwithrespecttotheoutputstreamchannelalignment.Although
all input data comes in at the same speed, delays can be caused by variable
path serial backplanes and variable path lengths which may be implemented
in large centralized and distributed switching systems. Because data is often
delayed, this feature is useful in compensating for the skew between input
streams.
Each input stream can have its own delay offset value by programming the
frameinputoffsetregisters(FOR,Table8).Themaximumallowableskewis+7.5
master clock (C32i) periods forward with a resolution of ½ clock period, see
Table 9. The output frame cannot be adjusted.
SERIAL INPUT FRAME ALIGNMENT EVALUATION
The IDT72V73260 provides the Frame Evaluation input to determine
differentdatainputdelayswithrespecttotheframepulseF32i.Ameasurement
cycleisstartedbysettingtheStartFrameEvaluation bitoftheControlRegister
LOW for at least one frame. When the Start Frame Evaluation bit in the Control
RegisterischangedfromLOWtoHIGH,theevaluationstarts.Twoframeslater,
the Complete Frame Evaluation bit of the Frame Alignment Register changes
from LOW to HIGH to signal that a valid offset measurement is ready to be read
from bits 0 to 12 of the Frame Alignment Register . The Start Frame Evaluation
bit must be set to zero before a new measurement cycle is started.
InST-BUS®mode,thefallingedgeoftheframemeasurementsignal(Frame
Evaluation) is evaluated against the falling edge of the ST-BUS ® frame pulse.
InGCImode,therisingedgeofFrameEvaluationisevaluatedagainsttherising
edge of the GCI frame pulse. See Table 7 and Figure 1 for the description of
the Frame Alignment Register.
MEMORY BLOCK PROGRAMMING
The IDT72V73260 provides users with the capability of initializing the entire
Connection Memory block in two frames. To set bits 14 and 15 of every
Connection Memory location, first program the desired pattern in the Block
ProgrammingDataBits(BPD1-0),locatedinbits7and8 oftheControlRegister.
The block programming mode is enabled by setting the Memory Block
Program bitoftheControlRegisterHIGH.WhentheBlockProgrammingEnable
bit of the Control Register is set to HIGH, the Block Programming data will be
loaded into the bits 14 and 15 of every Connection Memory location. The other
ConnectionMemorybits(bit0tobit13)areloadedwithzeros.Whenthememory
block programming is complete, the device resets the Block Programming
Enable, BPD 1-0 and Memory Block Program bits to zero.


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