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IDT5V9352PRI Datasheet(PDF) 1 Page - Integrated Device Technology

Part # IDT5V9352PRI
Description  3.3V/2.5V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT5V9352PRI Datasheet(HTML) 1 Page - Integrated Device Technology

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INDUSTRIALTEMPERATURERANGE
IDT5V9352
3.3V/2.5V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER
÷6
÷4
÷2
÷2
VCO
1
0
1
0
CCLK
QB3
QB0
QB1
QB2
QA0
QA1
QA2
QA3
QA4
QC1
QC0
1
0
BANK A
BANK B
BANK C
1
0
1
0
PLL_En
REFCLK
FBIN
VCO_SEL
fSELA
fSELB
MR/OE
fSELC
PLL
REF
FB
AUGUST 2003
2003
Integrated Device Technology, Inc.
DSC 5973/18
c
IDT5V9352
INDUSTRIAL TEMPERATURE RANGE
3.3V/2.5V PHASE-LOCK
LOOP CLOCK DRIVER
ZERO DELAY BUFFER
The 5V9352 is a low-skew, low-jitter, phase-lock loop (PLL) clock driver
targeted for high performance clock tree applications. It uses a PLL to
precisely align, in both frequency and phase. The 5V9352 operates at 2.5V
and 3.3V.
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION:
The 5V9352 features three banks of individually configurable outputs.
The banks are configured with five, four, and two outputs. The internal
divide circuitry allows for output frequency ratios of 1:1, 2:1, 3:1, and 3:2:1.
The output frequency relationship is controlled by the fSEL frequency
control pins. The fSEL pins, as well as other inputs, are LVCMOS/LVTTL
compatibleinputs
Unlike many products containing PLLs, the 5V9352 does not require
external RC networks. The loop filter for the PLL is included on-chip,
minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the 5V9352 requires a stabilization
time to achieve phase lock of the feedback signal to the reference signal.
This stabilization time is required, following power up and application of a
fixed-frequency, fixed-phase signal at REFCLK, as well as following any
changes to the PLL reference or feedback signals. The PLL can be
bypassed for test purposes by setting the PLL_EN to high.
The 5V9352 is available in Industrial temperature range (-40°C to
+85°C).
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FEATURES:
• Phase-lock loop clock distribution for high performance clock
tree applications
• Output enable bank control
• External feedback (FBIN) pin is used to synchronize the
outputs to the clock input signal
• No external RC network required for PLL loop stability
• Operates at 3.3V/2.5V VCC
• Spread Spectrum Compatible
• Operating frequency up to 200MHz
• Compatible with Motorola MPC9352
• Available in 32-pin TQFP package


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