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HY62SF16201ALLF Datasheet(PDF) 2 Page - Hynix Semiconductor |
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HY62SF16201ALLF Datasheet(HTML) 2 Page - Hynix Semiconductor |
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2 / 10 page  HY62SF16201A Rev.06 /Mar. 2002 2 DESCRIPTION The HY62SF16201A is a high speed, low power and 2M bit full CMOS SRAM organized as 131,072 words by 16bit. The HY62SF16201A uses high performance full CMOS process technology and designed for high speed low power circuit technology. It is particularly well suited for used in high density low power system application. This device has a data retention mode that guarantees data to remain valid at a minimum power supply voltage of 1.2V. FEATURES • Fully static operation and Tri-state output • TTL compatible inputs and outputs • Battery backup(LL-part) -. 1.2V(min) data retention • Standard pin configuration -. 48-FBGA Product Voltage Speed Operation Standby Current(uA) Temperature No. (V) (ns) Current/Icc(mA) LL SL ( °C) HY62SF16201A 1.7~2.3V 85/100/120 3 3 1 0~70 HY62SF16201A-I 1.7~2.3V 85/100/120 3 3 1 -40~85(I) Notes : 1. Blank : Commercial, I : Industrial 2. Current value is max. PIN CONNECTION BLOCK DIAGRAM /LB IO9 IO10 /OE A0 A1 A2 NC /UB A3 A4 /CS IO1 IO11 A5 A6 IO2 IO3 Vss IO12 NC A7 IO4 Vcc Vcc IO13 NC A16 IO5 Vss IO15 IO14 A14 A15 IO6 IO7 IO16 NC A12 A13 /WE IO8 NC A8 A9 A10 A11 NC 48-FBGA(Top View) PIN DESCRIPTION Pin Name Pin Function Pin Name Pin Function /CS Chip Select I/O1~I/O16 Data Inputs / Outputs /WE Write Enable A0~A16 Address Inputs /OE Output Enable Vcc Power( 1.7V ~ 2.3V ) /LB Lower Byte Control(I/O1~I/O8) Vss Ground /UB Upper Byte Control(I/O9~I/O16) NC No Connection MEMORY ARRAY 128K x 16 ROW DECODER I/O1 I/O16 A0 A16 /CS /OE /LB /UB /WE |
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