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SLG88103 Datasheet(PDF) 10 Page - Dialog Semiconductor |
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SLG88103 Datasheet(HTML) 10 Page - Dialog Semiconductor |
10 / 22 page 000-0088103/4-101 Page 10 of 22 SLG88103/4 Applications Information The SLG88103/4 operates on a 1.71 V to 5.5 V power supply over a wide industrial temperature range from -40 °C to 85 °C. This dual/quad op amp chip has two/four active low enable pins used to individually power-up / power-down each op amp. Its com- mon-mode range extends from 0 to VDD and its output swings from rail-to-rail. Input Protection Voltage spikes need to be controlled at the inputs of each operational amplifier in order to avoid damaging the device. Electrical events like electrostatic discharge can produce large voltages at these nodes. The SLG88103/4 has internal circuitry to protect the device from these events. If VIN exceeds VDD or drops below VSS, additional currents will flow through the internal ESD diodes and can damage the device even if the supplies are turned off. In this case we recommend placing a resistor in series to the input to limit current through the internal ESD diodes to 5 mA (or preferably less). Driving Capacitive Loads Capacitive loads degrade circuit stability by decreasing the phase margin and bandwidth of the operational amplifier circuit. The SLG88103/4 can drive capacitive loads up to 10 nF at low loads. The amplifier’s output impedance and the capacitive load add phase lag to the system. This phase lag creates gain peaking in the frequency response and peaking/ringing in the output’s transient response. When large capacitive loads need to be driven, isolation resistors need to be used to increase the phase margin. This is done by increasing the output load impedance at higher frequencies. After selecting an isolation resistor value, verify that the frequency peaking and transient overshoot and ringing have been reduced. Fig 31. ESD Protection . Fig 32. Capacitive Load Test Circuit. |
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