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SLG46824 Datasheet(PDF) 36 Page - Dialog Semiconductor

Part No. SLG46824
Description  GreenPAK Programmable Mixed Signal Matrix with In System
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Maker  DIALOG [Dialog Semiconductor]
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SLG46824 Datasheet(HTML) 36 Page - Dialog Semiconductor

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Datasheet
31-Jan-2018
CFR0011-120-01
Revision 2.3
36 of 152
© 2018 Dialog Semiconductor
SLG46824
GreenPAK Programmable Mixed Signal Matrix with In System
Programmability
PRELIMINARY
7
Combination Function Macrocells
The SLG46824 has 11 combination function macrocells that can serve more than one logic or timing function. In each case, they
can serve as a Look Up Table (LUT), or as another logic or timing function. See the list below for the functions that can be
implemented in these macrocells;
Three macrocells that can serve as either 2-bit LUT or as D Flip Flop
Six macrocells that can serve as either 3-bit LUTs or as D Flip Flops with Set/Reset Input
One macrocell that can serve as either 3-bit LUT or as Pipe Delay/Ripple Counter
One macrocell that can serve as either 2-bit LUT or as Programmable Pattern Generator (PGEN)
Inputs/Outputs for the 11 combination function macrocells are configured from the connection matrix with specific logic functions
being defined by the state of NVM bits.
When used as a LUT to implement combinatorial logic functions, the outputs of the LUTs can be configured to any user defined
function, including the following standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR).
7.1 2-BIT LUT OR D FLIP FLOP MACROCELLS
There are three macrocells that can serve as either 2-bit LUT or as D Flip Flop. When used to implement LUT functions, the
2-bit LUT takes in two input signals from the connection matrix and produce a single output, which goes back into the connection
matrix. When used to implement D Flip Flop function, the two input signals from the connection matrix go to the data (D) and clock
(CLK) inputs for the Flip Flop, with the output going back to the connection matrix.
The operation of the D Flip-Flop and Latch will follow the functional descriptions below:
DFF: CLK is rising edge triggered, then Q = D; otherwise Q will not change
Latch: when CLK is Low, then Q = D; otherwise Q remains its previous value (input D has no effect on the output, when CLK is
High)
Figure 9: 2-bit LUT0 or DFF0
DFF0
CLK
D
2-bit LUT0 OUT
IN0
IN1
To Connection Matrix
Input <14>
4-bits NVM
From Connection Matrix Output <1>
1-bit NVM
reg <1155:1152>
reg <1232>
From Connection Matrix Output <0>
Q/nQ
reg <1155> DFF or Latch Select
reg <1154> Output Select (Q or nQ)
reg <1153> DFF Initial Polarity Select
LUT Truth
Table
DFF/Latch
Registers
S0
S1
S0
S1
S0
S1
0: 2-bit LUT0 IN1
1: DFF0 Data
0: 2-bit LUT0 Out
1: DFF0 Out
0: 2-bit LUT0 IN0
1: DFF0 CLK


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