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SLG46824 Datasheet(PDF) 33 Page - Dialog Semiconductor

Part No. SLG46824
Description  GreenPAK Programmable Mixed Signal Matrix with In System
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Maker  DIALOG [Dialog Semiconductor]
Homepage  http://www.dialog-semiconductor.com/
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SLG46824 Datasheet(HTML) 33 Page - Dialog Semiconductor

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Datasheet
31-Jan-2018
CFR0011-120-01
Revision 2.3
33 of 152
© 2018 Dialog Semiconductor
SLG46824
GreenPAK Programmable Mixed Signal Matrix with In System
Programmability
PRELIMINARY
reg <245:240>
MULTFUNC_8BIT_3: IN0 of LUT3_9 or Clock Input of DFF12;
Delay3 Input (or Counter3 nRST Input)
40
reg <251:246>
MULTFUNC_8BIT_3: IN1 of LUT3_9 or nRST (nSET) of DFF12;
Delay3 Input (or Counter3 nRST Input) or Delay/Counter3 External Clock Source
41
reg <257:252>
MULTFUNC_8BIT_3: IN2 of LUT3_9 or Data Input of DFF12;
Delay3 Input (or Counter3 nRST Input)
42
reg <263:258>
MULTFUNC_8BIT_4: IN0 of LUT3_10 or Clock Input of DFF13;
Delay4 Input (or Counter4 nRST Input)
43
reg <269:264>
MULTFUNC_8BIT_4: IN1 of LUT3_10 or nRST (nSET) of DFF13;
Delay4 Input (or Counter4 nRST Input) or Delay/Counter4 External Clock Source
44
reg <275:270>
MULTFUNC_8BIT_4: IN2 of LUT3_10 or Data Input of DFF13;
Delay4 Input (or Counter4 nRST Input)
45
reg <281:276>
MULTFUNC_8BIT_5: IN0 of LUT3_11 or Clock Input of DFF14;
Delay5 Input (or Counter5 nRST Input)
46
reg <287:282>
MULTFUNC_8BIT_5: IN1 of LUT3_11 or nRST (nSET) of DFF14;
Delay5 Input (or Counter5 nRST Input) or Delay/Counter5 External Clock Source
47
reg <293:288>
MULTFUNC_8BIT_5: IN2 of LUT3_11 or Data Input of DFF14;
Delay5 Input (or Counter5 nRST Input)
48
reg <299:294>
MULTFUNC_8BIT_6: IN0 of LUT3_12 or Clock Input of DFF15;
Delay6 Input (or Counter6 nRST Input)
49
reg <305:300>
MULTFUNC_8BIT_6: IN1 of LUT3_12 or nRST (nSET) of DFF15;
Delay6 Input (or Counter6 nRST Input) or Delay/Counter6 External Clock Source
50
reg <311:306>
MULTFUNC_8BIT_6: IN2 of LUT3_12 or Data Input of DFF15;
Delay6 Input (or Counter6 nRST Input)
51
reg <317:312>
MULTFUNC_8BIT_7: IN0 of LUT3_13 or Clock Input of DFF16;
Delay7 Input (or Counter7 nRST Input)
52
reg <323:318>
MULTFUNC_8BIT_7: IN1 of LUT3_13 or nRST (nSET) of DFF16;
Delay7 Input (or Counter7 nRST Input) or Delay/Counter7 External Clock Source
53
reg <329:324>
MULTFUNC_8BIT_7: IN2 of LUT3_13 or Data Input of DFF16;
Delay7 Input (or Counter7 nRST Input)
54
reg <335:330>
Filter/Edge detect input
55
reg <341:336>
Programmable delay/edge detect input
56
reg <347:342>
OSC2 ENABLE from matrix
57
reg <353:348>
OSC0 ENABLE from matrix
58
reg <359:354>
OSC1 ENABLE matrix
59
reg <365:360>
Reserved
60
reg <371:366>
BG power down from matrix
61
reg <377:372>
Reserved
62
reg <383:378>
Reserved
63
reg <389:384>
pd of ACMP0L from matrix
64
reg <395:390>
pd of ACMP1L from matrix
65
reg <401:396>
Reserved
66
reg <407:402>
IO0 Digital Output
67
reg <413:408>
IO1 Digital Output
68
Table 20: Matrix Output Table
Register Bit
Address
Matrix Output Signal Function
Matrix Output
Number


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