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SLG46824 Datasheet(PDF) 32 Page - Dialog Semiconductor

Part No. SLG46824
Description  GreenPAK Programmable Mixed Signal Matrix with In System
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Maker  DIALOG [Dialog Semiconductor]
Homepage  http://www.dialog-semiconductor.com/
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SLG46824 Datasheet(HTML) 32 Page - Dialog Semiconductor

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Datasheet
31-Jan-2018
CFR0011-120-01
Revision 2.3
32 of 152
© 2018 Dialog Semiconductor
SLG46824
GreenPAK Programmable Mixed Signal Matrix with In System
Programmability
PRELIMINARY
reg <59:54>
IN1 of LUT3_0 or Data Input of DFF3
9
reg <65:60>
IN2 of LUT3_0 or nRST(nSET) of DFF3
10
reg <71:66>
IN0 of LUT3_1 or Clock Input of DFF4
11
reg <77:72>
IN1 of LUT3_1 or Data Input of DFF4
12
reg <83:78>
IN2 of LUT3_1 or nRST(nSET) of DFF4
13
reg <89:84>
IN0 of LUT3_2 or Clock Input of DFF5
14
reg <95:90>
IN1 of LUT3_2 or Data Input of DFF5
15
reg <101:96>
IN2 of LUT3_2 or nRST(nSET) of DFF5
16
reg <107:102>
IN0 of LUT3_3 or Clock Input of DFF6
17
reg <113:108>
IN1 of LUT3_3 or Data Input of DFF6
18
reg <119:114>
IN2 of LUT3_3 or nRST(nSET) of DFF6
19
reg <125:120>
IN0 of LUT3_4 or Clock Input of DFF7
20
reg <131:126>
IN1 of LUT3_4 or Data Input of DFF7
21
reg <137:132>
IN2 of LUT3_4 or nRST(nSET) of DFF7
22
reg <143:138>
IN0 of LUT3_5 or Clock Input of DFF8
23
reg <149:144>
IN1 of LUT3_5 or Data Input of DFF8
24
reg <155:150>
IN2 of LUT3_5 or nRST(nSET) of DFF8
25
reg <161:156>
IN0 of LUT3_6 or Input of Pipe Delay or UP Signal of RIPP CNT
26
reg <167:162>
IN1 of LUT3_6 or nRST of Pipe Delay or STB of RIPP CNT
27
reg <173:168>
IN2 of LUT3_6 or Clock of Pipe Delay_RIPP_CNT
28
reg <179:174>
Reserved
29
reg <185:180>
MULTFUNC_16BIT_0: IN0 of LUT4_0 or Clock Input of DFF9;
Delay0 Input (or Counter0 RST/SET Input)
30
reg <191:186>
MULTFUNC_16BIT_0: IN1 of LUT4_0 or nRST of DFF9;
Delay0 Input (or Counter0 nRST Input) or Delay/Counter0 External Clock Source
31
reg <197:192>
MULTFUNC_16BIT_0: IN2 of LUT4_0 or nSET of DFF9;
Delay0 Input (or Counter0 nRST Input) or Delay/Counter0 External Clock Source or
KEEP Input of FSM0
32
reg <203:198>
MULTFUNC_16BIT_0: IN3 of LUT4_0 or Data Input of DFF9;
Delay0 Input (or Counter0 nRST Input) or UP Input of FSM0
33
reg <209:204>
MULTFUNC_8BIT_1: IN0 of LUT3_7 or Clock Input of DFF10;
Delay1 Input (or Counter1 nRST Input)
34
reg <215:210>
MULTFUNC_8BIT_1: IN1 of LUT3_7 or nRST (nSET) of DFF10;
Delay1 Input (or Counter1 nRST Input) or Delay/Counter1 External Clock Source
35
reg <221:216>
MULTFUNC_8BIT_1: IN2 of LUT3_7 or Data Input of DFF10;
Delay1 Input (or Counter1 nRST Input)
36
reg <227:222>
MULTFUNC_8BIT_2: IN0 of LUT3_8 or Clock Input of DFF11;
Delay2 Input (or Counter2 nRST Input);
37
reg <233:228>
MULTFUNC_8BIT_2: IN1 of LUT3_8 or nRST (nSET) of DFF11;
Delay2 Input (or Counter2 nRST Input) or Delay/Counter2 External Clock Source
38
reg <239:234>
MULTFUNC_8BIT_2: IN2 of LUT3_8 or Data Input of DFF11;
Delay2 Input (or Counter2 nRST Input)
39
Table 20: Matrix Output Table
Register Bit
Address
Matrix Output Signal Function
Matrix Output
Number


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