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SLG46824 Datasheet(PDF) 2 Page - Dialog Semiconductor

Part No. SLG46824
Description  GreenPAK Programmable Mixed Signal Matrix with In System
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Maker  DIALOG [Dialog Semiconductor]
Homepage  http://www.dialog-semiconductor.com/
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SLG46824 Datasheet(HTML) 2 Page - Dialog Semiconductor

 
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Datasheet
31-Jan-2018
CFR0011-120-01
Revision 2.3
2 of 152
© 2018 Dialog Semiconductor
SLG46824
GreenPAK Programmable Mixed Signal Matrix with In System
Programmability
PRELIMINARY
Contents
1 Block Diagram ......................................................................................................................................................................7
2 Pinout ....................................................................................................................................................................................8
2.1 Pin Configuration - STQFN- 20L ............................................................................................................................8
2.2 Pin Configuration - TSSOP-20L .............................................................................................................................9
3 Characteristics ...................................................................................................................................................................13
3.1 Absolute Maximum Ratings .................................................................................................................................13
3.2 Recommended Operating Conditions .................................................................................................................13
3.3 Electrical Characteristics ......................................................................................................................................13
3.4 Timing Characteristics .........................................................................................................................................17
3.5 OSC Characteristics .............................................................................................................................................19
3.6 ACMP Specifications ............................................................................................................................................21
4 User Programmability ........................................................................................................................................................23
5 IO Pins .................................................................................................................................................................................24
5.1 IO Pins .................................................................................................................................................................24
5.2 GPIO Pins ............................................................................................................................................................24
5.3 GPO Pins .............................................................................................................................................................24
5.4 GPI Pins ...............................................................................................................................................................24
5.5 Pull Up/Down Resistors .......................................................................................................................................24
5.6 Fast Pull-up/down during Power up .....................................................................................................................24
5.7 I2C Mode IO Structure (VDD or VDD2) ...............................................................................................................25
5.8 Matrix OE IO Structure (VDD or VDD2) ...............................................................................................................26
5.9 Register OE IO Structure (VDD or VDD2) ...........................................................................................................27
5.10 Register OE IO Structure (VDD or VDD2) .........................................................................................................28
6 Connection Matrix ..............................................................................................................................................................29
6.1 Matrix Input Table ................................................................................................................................................30
6.2 Matrix Output Table .............................................................................................................................................31
6.3 Connection Matrix Virtual Inputs ..........................................................................................................................34
6.4 Connection Matrix Virtual Outputs .......................................................................................................................35
7 Combination Function Macrocells ....................................................................................................................................36
7.1 2-Bit LUT or D Flip Flop Macrocells .....................................................................................................................36
7.4 3-Bit LUT or Pipe Delay / Ripple Counter Macrocell ............................................................................................49
8 Multi-Function Macrocells .................................................................................................................................................54
8.1 3-Bit LUT or 8- Bit Counter / Delay Macrocells ....................................................................................................54
8.2 CNT/DLY/FSM Timing Diagrams .........................................................................................................................63
8.3 4-Bit LUT or 16-Bit Counter / Delay Macrocell .....................................................................................................71
9 Analog Comparators ..........................................................................................................................................................73
9.1 ACMP0L Block Diagram ....................................................................................................................................74
9.2 ACMP1L Block Diagram .....................................................................................................................................75
10 Programmable Delay / Edge Detector ............................................................................................................................76
10.1 Programmable Delay Timing Diagram - Edge Detector Output .........................................................................76
11 Additional Logic Function. Deglitch Filter .....................................................................................................................77
12 Voltage Reference (VREF) ...............................................................................................................................................78
12.1 Voltage Reference Overview .............................................................................................................................78
12.2 VREF Selection Table .......................................................................................................................................78
12.3 VREF Block Diagram ........................................................................................................................................79
13 Clocking ............................................................................................................................................................................80
13.1 Osc general description .....................................................................................................................................80
13.2 Oscillator0 (2.048 kHz) .......................................................................................................................................81
13.3 Oscillator1 (2.048 MHz) .....................................................................................................................................82
13.4 Oscillator2 (25 MHz) ..........................................................................................................................................83
13.5 Clock Scheme ...................................................................................................................................................84
13.6 External Clocking ...............................................................................................................................................84
14 Power On Reset (POR) .....................................................................................................................................................85
14.1 General Operation ..............................................................................................................................................85
14.2 POR Sequence ..................................................................................................................................................86
14.3 Macrocells Output States During POR Sequence .............................................................................................86


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