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SLG46824 Datasheet(PDF) 16 Page - Dialog Semiconductor

Part No. SLG46824
Description  GreenPAK Programmable Mixed Signal Matrix with In System
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Maker  DIALOG [Dialog Semiconductor]
Homepage  http://www.dialog-semiconductor.com/
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SLG46824 Datasheet(HTML) 16 Page - Dialog Semiconductor

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Datasheet
31-Jan-2018
CFR0011-120-01
Revision 2.3
16 of 152
© 2018 Dialog Semiconductor
SLG46824
GreenPAK Programmable Mixed Signal Matrix with In System
Programmability
PRELIMINARY
Table 5: I2C Specifications
IOL
LOW-Level Output Current
NMOS OD, VOL = 0.15 V, 1X Drive,
VDD = 2.5 V +/- 8 % (Note 2)
1.37
2.53
--
mA
NMOS OD, VOL = 0.4 V, 1X Drive,
VDD = 3.3 V +/- 10 % (Note 2)
7.31
12.37
--
mA
NMOS OD, VOL = 0.4 V, 1X Drive,
VDD = 5 V +/- 10 % (Note 2)
10.82
17.38
--
mA
NMOS OD, VOL = 0.15 V, 2X Drive,
VDD2 = 1.8 V +/- 5 %
2.75
5.07
--
mA
NMOS OD, VOL = 0.15 V, 2X Drive,
VDD = 2.5 V +/- 8 % (Note 2)
2.75
5.07
--
mA
NMOS OD, VOL = 0.4 V, 2X Drive,
VDD = 3.3 V +/- 10 % (Note 2)
14.54
24.74
--
mA
NMOS OD, VOL = 0.4 V, 2X Drive,
VDD = 5 V +/- 10 % (Note 2)
17.34
34.76
--
mA
TSU
Startup Time
From VDD rising past PONTHR
--
1.30
2.15
ms
PONTHR
Power On Threshold
VDD Level Required to Start Up the Chip
1.63
1.85
2.04
V
POFFTHR Power Off Threshold
VDD Level Required to Switch Off the
Chip
1.01
1.26
1.49
V
RPULL
Pull Up or Pull Down
Resistance
1 M for Pull Up: VIN = GND;
for Pull Down: VIN = VDD (Note 2)
0.74
1.10
1.50
M
100 k for Pull Up: VIN = GND;
for Pull Down: VIN = VDD (Note 2)
88
107
132
k
10 k For Pull Up: VIN = GND;
for Pull Down: VIN = VDD (Note 2)
710
17
k
CIN
Input Capacitance
4
pF
Note 2: IOs 0 to 6, SCL, SDA are powered from VDD and IOs 7 to 14 are powered from VDD2.
Note 3: No hysteresis.
Symbol
Parameter
Condition/Note
Fast-Mode
Fast-Mode Plus
Unit
Min
Typ
Max
Min
Typ
Max
FSCL
Clock Frequency, SCL
VDD = 2.3 V to 5.5 V
--
--
400
--
--
1000 kHz
tLOW
Clock Pulse Width Low
VDD = 2.3 V to 5.5 V
1300
--
--
500
--
--
ns
tHIGH
Clock Pulse Width High
VDD = 2.3 V to 5.5 V
600
--
--
260
--
--
ns
tI
Input Filter Spike Suppression
(SCL, SDA)
VDD = 2.3 V to 5.5 V
--
--
50
--
--
50
ns
tAA
Clock Low to Data Out Valid
VDD = 2.3 V to 5.5 V
--
--
900
--
--
450
ns
tBUF
Bus Free Time between Stop
and Start
VDD = 2.3 V to 5.5 V
1300
--
--
500
--
--
ns
tHD_STA
Start Hold Time
VDD = 2.3 V to 5.5 V
600
--
--
260
--
--
ns
tSU_STA
Start Set-up Time
VDD = 2.3 V to 5.5 V
600
--
--
260
--
--
ns
tHD_DAT
Data Hold Time
VDD = 2.3 V to 5.5 V
0
--
--
0
--
--
ns
tSU_DAT
Data Set-up Time
VDD = 2.3 V to 5.5 V
100
--
--
50
--
--
ns
tR
Inputs Rise Time
VDD = 2.3 V to 5.5 V
--
--
300
--
--
120
ns
tF
Inputs Fall Time
VDD = 2.3 V to 5.5 V
--
--
300
--
--
120
ns
tSU_STD
Stop Set-up Time
VDD = 2.3 V to 5.5 V
600
--
--
260
--
--
ns
tDH
Data Out Hold Time
VDD = 2.3 V to 5.5 V
50
--
--
50
--
--
ns
Symbol
Parameter
Condition
Min
Typ
Max
Unit


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