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SLG46824 Datasheet(PDF) 100 Page - Dialog Semiconductor

Part No. SLG46824
Description  GreenPAK Programmable Mixed Signal Matrix with In System
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Maker  DIALOG [Dialog Semiconductor]
Homepage  http://www.dialog-semiconductor.com/
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SLG46824 Datasheet(HTML) 100 Page - Dialog Semiconductor

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Datasheet
31-Jan-2018
CFR0011-120-01
Revision 2.3
100 of 152
© 2018 Dialog Semiconductor
SLG46824
GreenPAK Programmable Mixed Signal Matrix with In System
Programmability
PRELIMINARY
17
Register Definitions
Address
Signal Function
Register Bit Definition
I2C Interface
Byte
Register Bit
Read Write
Matrix Output
00
reg<5:0>
Matrix OUT0
IN0 of LUT2_0 or Clock Input of DFF0
00
reg<11:6>
Matrix OUT1
IN1 of LUT2_0 or Data Input of DFF0
01
01
reg<17:12>
Matrix OUT2
IN0 of LUT2_3 or Clock Input of PGEN
02
02
reg<23:18>
Matrix OUT3
IN1 of LUT2_3 or nRST of PGEN
03
reg<29:24>
Matrix OUT4
IN0 of LUT2_1 or Clock Input of DFF1
03
reg<35:30>
Matrix OUT5
IN1 of LUT2_1 or Data Input of DFF1
04
04
reg<41:36>
Matrix OUT6
IN0 of LUT2_2 or Clock Input of DFF2
05
05
reg<47:42>
Matrix OUT7
IN1 of LUT2_2 or Data Input of DFF2
06
reg<53:48>
Matrix OUT8
IN0 of LUT3_0 or Clock Input of DFF3
06
reg<59:54>
Matrix OUT9
IN1 of LUT3_0 or Data Input of DFF3
07
07
reg<65:60>
Matrix OUT10
IN2 of LUT3_0 or nRST(nSET) of DFF3
08
reg<71:66>
Matrix OUT11
IN0 of LUT3_1 or Clock Input of DFF4
09
reg<77:72>
Matrix OUT12
IN1 of LUT3_1 or Data Input of DFF4
09
reg<83:78>
Matrix OUT13
IN2 of LUT3_1 or nRST(nSET) of DFF4
0A
0A
reg<89:84>
Matrix OUT14
IN0 of LUT3_2 or Clock Input of DFF5
0B
0B
reg<95:90>
Matrix OUT15
IN1 of LUT3_2 or Data Input of DFF5
0C
reg<101:96>
Matrix OUT16
IN2 of LUT3_2 or nRST(nSET) of DFF5
0C
reg<107:102>
Matrix OUT17
IN0 of LUT3_3 or Clock Input of DFF6
0D
0D
reg<113:108>
Matrix OUT18
IN1 of LUT3_3 or Data Input of DFF6
0E
0E
reg<119:114>
Matrix OUT19
IN2 of LUT3_3 or nRST(nSET) of DFF6
0F
reg<125:120>
Matrix OUT20
IN0 of LUT3_4 or Clock Input of DFF7
0F
reg<131:126>
Matrix OUT21
IN1 of LUT3_4 or Data Input of DFF7
10
10
reg<137:132>
Matrix OUT22
IN2 of LUT3_4 or nRST(nSET) of DFF7
11
11
reg<143:138>
Matrix OUT23
IN0 of LUT3_5 or Clock Input of DFF8
12
reg<149:144>
Matrix OUT24
IN1 of LUT3_5 or Data Input of DFF8
12
reg<155:150>
Matrix OUT25
IN2 of LUT3_5 or nRST(nSET) of DFF8
13
13
reg<161:156>
Matrix OUT26
IN0 of LUT3_6 or Input of Pipe Delay or
UP Signal of RIPP CNT
14


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