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SLG46824 Datasheet(PDF) 95 Page - Dialog Semiconductor

Part No. SLG46824
Description  GreenPAK Programmable Mixed Signal Matrix with In System
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Maker  DIALOG [Dialog Semiconductor]
Homepage  http://www.dialog-semiconductor.com/
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SLG46824 Datasheet(HTML) 95 Page - Dialog Semiconductor

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Datasheet
31-Jan-2018
CFR0011-120-01
Revision 2.3
95 of 152
© 2018 Dialog Semiconductor
SLG46824
GreenPAK Programmable Mixed Signal Matrix with In System
Programmability
PRELIMINARY
See Section
17 for detailed information on all registers.
15.5.1 I2C Serial Reset Command
If I2C serial communication is established with the device, it is possible to reset the device to initial power up conditions, including
configuration of all macrocells, and all connections provided by the Connection Matrix. This is implemented by setting reg<1601>
I2C reset bit to “1”, which causes the device to re-enable the Power On Reset (POR) sequence, including the reload of all register
data from NVM. During the POR sequence, the outputs of the device will be in tri-state. After the reset has taken place, the contents
of reg<1601> will be set to “0” automatically. Figure 67 illustrates the sequence of events for this reset function.
15.5.2 I2C Additional Options
When Output latching during I2C write to the register configuration data (block address A10A9A8 = 000), reg<1602> = 1 allows
all PINs output value to be latched while register content is changing. It will protect the output change due to configuration process
during I2C write in case multiple register bytes are changed. Inputs and internal macrocells retain their status during I2C write.
See Section 17 for detailed information on all registers.
15.5.3 Reading Counter Data via I2C
The current count value in three counters in the device can be read via I2C. The counters that have this additional functionality
are 16-bit CNT0, and 8-bit counters CNT2 and CNT4.
15.5.4 I2C Expander
In addition to the eight Connection Matrix Virtual Inputs, the SLG46824 chip has four pins which can be used as an I2C Expander.
These four pins are IO0, IO5, IO6, and IO9.
Figure 67: Reset Command Timing
X
X
X
X
A
10
A
9
A
8
W
A
7
A
0
Control Byte
Word Address
Control
Code
Block
Address
Write bit
S
ACK
Acknowledge
bit
Start
bit
ACK D
7
D
0
Data
P
Stop
bit
Acknowledge
bit
SDA LINE
Bus Activity
Acknowledge
bit
ACK
Reset-bit register output
DFF output gated by stop signal
Internal POR for core only
Internal Reset bit
by I2C Stop Signal


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