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SLG46824 Datasheet(PDF) 89 Page - Dialog Semiconductor

Part No. SLG46824
Description  GreenPAK Programmable Mixed Signal Matrix with In System
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Maker  DIALOG [Dialog Semiconductor]
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SLG46824 Datasheet(HTML) 89 Page - Dialog Semiconductor

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Datasheet
31-Jan-2018
CFR0011-120-01
Revision 2.3
89 of 152
© 2018 Dialog Semiconductor
SLG46824
GreenPAK Programmable Mixed Signal Matrix with In System
Programmability
PRELIMINARY
15
I2C Serial Communications Macrocell
15.1 I2C SERIAL COMMUNICATIONS MACROCELL OVERVIEW
In the standard use case for the GreenPAK devices, the configuration choices made by the user are stored as bit settings in the
Non-Volatile Memory (NVM), and this information is transferred at startup time to volatile RAM registers that enable the configu-
ration of the macrocells. Other RAM registers in the device are responsible for setting the connections in the Connection Matrix
to route signals in the manner most appropriate for the user’s application.
The I2C Serial Communications Macrocell in this device allows an I2C bus Master to read and write this information via a serial
channel directly to the RAM registers, allowing the remote re-configuration of macrocells, and remote changes to signal chains
within the device.
An I2C bus Master is also able read and write other register bits that are not associated with NVM memory. As an example, the
input lines to the Connection Matrix can be read as digital register bits. These are the signal outputs of each of the macrocells in
the device, giving an I2C bus Master the capability to remotely read the current value of any macrocell.
The user has the flexibility to control read access and write access via registers bits reg<1795:1792>. See Section 16 for more
details on I2C read/write memory protection.
15.2 I2C SERIAL COMMUNICATIONS DEVICE ADDRESSING
Each command to the I2C Serial Communications macrocell begins with a Control Byte. The bits inside this Control Byte are
shown in Figure 60. After the Start bit, the first four bits are a control code. Each bit in a control code can be sourced independently
from the register or by value defined externally by IO5, IO4, IO3 and IO2. The LSB of the control code is defined by the value of
IO2, while the MSB is defined by the value of IO5. The address source (either register bit or PIN) for each bit in the control code
is defined by reg <1623:1620>. This gives the user flexibility on the chip level addressing of this device and other devices on the
same I2C bus.The default control code is 0001. The Block Address is the next three bits (A10,A9, A8), which will define the most
significant bits in the addressing of the data to be read or written by the command. The last bit in the Control Byte is the R/W bit,
which selects whether a read command or write command is requested, with a “1” selecting for a Read command, and a “0”
selecting for a Write command. This Control Byte will be followed by an Acknowledge bit (ACK), which is sent by this device to
indicate successful communication of the Control Byte data.
In the I2C-bus specification and user manual, there are two groups of eight addresses (0000 xxx and 1111 xxx) that are reserved
for the special functions, such as a system General Call address. If the user of this device choses to set the Control Code to either
“1111” or “0000” in a system with other slave device, please consult the I2C-bus specification and user manual to understand the
addressing and implementation of these special functions, to insure reliable operation.
In the read and write command address structure, there are a total of 11 bits of addressing, each pointing to a unique byte of
information, resulting in a total address space of 16K bytes. The valid addresses are shown in the memory map in Figure 70.
With the exception of the Current Address Read command, all commands will have the Control Byte followed by the Word
Address.
Figure 60: Basic Command Structure
X
X
X
X
A
10
A
9
A
8
R/W
A
7
A
0
Control Byte
Word Address
Control
Code
Block
Address
Read/Write bit
S
ACK
Acknowledge
bit
Start
bit


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