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SLG46824 Datasheet(PDF) 86 Page - Dialog Semiconductor

Part No. SLG46824
Description  GreenPAK Programmable Mixed Signal Matrix with In System
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Maker  DIALOG [Dialog Semiconductor]
Homepage  http://www.dialog-semiconductor.com/
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SLG46824 Datasheet(HTML) 86 Page - Dialog Semiconductor

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Datasheet
31-Jan-2018
CFR0011-120-01
Revision 2.3
86 of 152
© 2018 Dialog Semiconductor
SLG46824
GreenPAK Programmable Mixed Signal Matrix with In System
Programmability
PRELIMINARY
14.2 POR SEQUENCE
The POR system generates a sequence of signals that enable certain macrocells. The sequence is shown in Figure 57.
As can be seen from Figure 57 after the VDD has start ramping up and crosses the Power_ON threshold, first, the on-chip NVM
memory is reset. Next the chip reads the data from NVM, and transfers this information to a CMOS Latch that serves to configure
each macrocell, and the Connection Matrix which routes signals between macrocells. The third stage causes the reset of the input
pins, and then to enable them. After that, the LUTs are reset and become active. After LUTs the Delay cells, RC OSC, DFFs,
Latches and Pipe Delay are initialized. Only after all macrocells are initialized internal POR signal (POR macrocell output) goes
from LOW to HIGH. The last portion of the device to be initialized are the output pins, which transition from high impedance to
active at this point.
The typical time that takes to complete the POR sequence varies by device type in the GreenPAK family. It also depends on many
environmental factors, such as: slew rate, VDD value, temperature and even will vary from chip to chip (process influence).
14.3 MACROCELLS OUTPUT STATES DURING POR SEQUENCE
To have a full picture of SLG46824 operation during powering and POR sequence, review the overview the macrocell output
states during the POR sequence (Figure 58 describes the output signals states).
First, before the NVM has been reset, all macrocells have their output set to logic LOW (except the output pins which are in high
impedance state). On the next step, some of the macrocells start initialization: input pins output state becomes LOW; LUTs also
output LOW. Only P DLY macrocell configured as edge detector becomes active at this time. After that input pins are enabled.
Figure 57: POR Sequence
VDD
POR_NVM
(reset for NVM)
NVM_ready_out
POR_GPI
(reset for input enable)
POR_LUT
(reset for LUT output)
POR_CORE
(reset for DLY/RCO/DFF
/Latch/Pipe DLY
POR_OUT
(generate low to high to matrix)
POR_GPO
(reset for output enable)
t
t
t
t
t
t
t
t


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