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SLG46824 Datasheet(PDF) 85 Page - Dialog Semiconductor

Part No. SLG46824
Description  GreenPAK Programmable Mixed Signal Matrix with In System
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Maker  DIALOG [Dialog Semiconductor]
Homepage  http://www.dialog-semiconductor.com/
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SLG46824 Datasheet(HTML) 85 Page - Dialog Semiconductor

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Datasheet
31-Jan-2018
CFR0011-120-01
Revision 2.3
85 of 152
© 2018 Dialog Semiconductor
SLG46824
GreenPAK Programmable Mixed Signal Matrix with In System
Programmability
PRELIMINARY
14
Power On Reset (POR)
The SLG46824 has a power-on reset (POR) macrocell to ensure correct device initialization and operation of all macrocells in
the device. The purpose of the POR circuit is to have consistent behavior and predictable results when the VDD power is first
ramping to the device, and also while the VDD is falling during power-down. To accomplish this goal, the POR drives a defined
sequence of internal events that trigger changes to the states of different macrocells inside the device, and finally to the state of
the IOs.
14.1 GENERAL OPERATION
The SLG46824 is guaranteed to be powered down and non-operational when the VDD voltage (voltage on PIN1) is less than
Power Off Threshold (see in Table 4), but not less than -0.6 V. Another essential condition for the chip to be powered down is that
no voltage higher (Note 8) than the VDD voltage is applied to any other PIN. For example, if VDD voltage is 0.3 V, applying a
voltage higher than 0.3 V to any other PIN is incorrect, and can lead to incorrect or unexpected device behavior.
Note 8: There is a 0.6 V margin due to forward drop voltage of the ESD protection diodes.
To start the POR sequence in the SLG46824, the voltage applied on the VDD should be higher than the Power_ON threshold
(Note 9). The full operational VDD range for the SLG46824 is 2.3 V to 5.5 V. This means that the VDD voltage must ramp up to
the operational voltage value, but the POR sequence will start earlier, as soon as the VDD voltage rises to the Power_ON threshold.
After the POR sequence has started, the SLG46824 will have a typical period of time to go through all the steps in the sequence
(noted in the datasheet for that device), and will be ready and completely operational after the POR sequence is complete.
Note 9: The Power_ON threshold is defined in Table 4.
To power down the chip the VDD voltage should be lower than the operational and to guarantee that chip is powered down it
should be less than Power Off Threshold.
All PINs are in high impedance state when the chip is powered down and while the POR sequence is taking place. The last step
in the POR sequence releases the IO structures from the high impedance state, at which time the device is operational. The pin
configuration at this point in time is defined by the design programmed into the chip. Also as it was mentioned before the voltage
on PINs can’t be bigger than the VDD, this rule also applies to the case when the chip is powered on.


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