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SLG46824 Datasheet(PDF) 84 Page - Dialog Semiconductor

Part No. SLG46824
Description  GreenPAK Programmable Mixed Signal Matrix with In System
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Maker  DIALOG [Dialog Semiconductor]
Homepage  http://www.dialog-semiconductor.com/
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SLG46824 Datasheet(HTML) 84 Page - Dialog Semiconductor

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Datasheet
31-Jan-2018
CFR0011-120-01
Revision 2.3
84 of 152
© 2018 Dialog Semiconductor
SLG46824
GreenPAK Programmable Mixed Signal Matrix with In System
Programmability
PRELIMINARY
13.5 CLOCK SCHEME
13.6 EXTERNAL CLOCKING
The SLG46824 supports several ways to use an external, higher accuracy clock as a reference source for internal operations.
13.6.1 IO0 Source for Oscillator0 (2.048 kHz)
When reg<1042> is set to 1, an external clocking signal on IO0 will be routed in place of the internal oscillator derived 2.048 kHz
clock source. See Figure 53.The high and low limits for frequency that can be selected are TBD MHz and TBD MHz.
13.6.2 IO10 Source for Oscillator1 (2.048 MHz)
When reg<1026> is set to 1, an external clocking signal on IO10 will be routed in place of the internal oscillator derived 2.048 MHz
clock source. See Figure 54. The high and low limits for frequency that can be selected are TBD MHz and TBD MHz.
13.6.3 IO8 Source for Oscillator2 (25 MHz)
When reg<1034> is set to 1, an external clocking signal on IO8 will be routed in place of the internal oscillator derived 25 MHz
clock source. See Figure 55. The high and low limits for frequency that can be selected are TBD MHz and TBD MHz.
Figure 56: Clock Scheme
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CNT/DLY/
ONESHOT/
FREQ_DET/
DLY_EDGE_DET
CNT overflow
Div8
Div64
Div512
Div32768
Div4096
Div262144
Div8
Div64
Div512
Div4
25 MHz Pre-divided clock
2.048 MHz Pre-divided clock
2.048 kHz Pre-divided clock
CNT (x-1) overflow
from Connection Matrix Out
(separate for each CNT/DLY macrocell)
reg <3:0>
CNT0/CNT1/CNT2/CNT3/
CNT4/CNT5/CNT6/CNT7


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