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SLG46824 Datasheet(PDF) 71 Page - Dialog Semiconductor

Part No. SLG46824
Description  GreenPAK Programmable Mixed Signal Matrix with In System
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Maker  DIALOG [Dialog Semiconductor]
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SLG46824 Datasheet(HTML) 71 Page - Dialog Semiconductor

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Datasheet
31-Jan-2018
CFR0011-120-01
Revision 2.3
71 of 152
© 2018 Dialog Semiconductor
SLG46824
GreenPAK Programmable Mixed Signal Matrix with In System
Programmability
PRELIMINARY
8.3 4-BIT LUT OR 16-BIT COUNTER / DELAY MACROCELL
There is one macrocell that can serve as either 4-bit LUT or as 16-bit Counter / Delay. When used to implement LUT function,
the 4-bit LUT takes in four input signals from the Connection Matrix and produces a single output, which goes back into the
Connection Matrix or can be connected to CNT/DLY’s input or LUT/DFF’s input. When used to implement 16-Bit Counter / Delay
function, two of the four input signals from the connection matrix go to the external clock (ext_CLK) and reset (DLY_in/CNT_Reset)
for the counter/delay, with the output going back to the connection matrix.
This macrocell has an optional Finite State Machine (FSM) function. There are two additional matrix inputs for Up and Keep to
support FSM functionality.
This macrocell can also operate in a one-shot mode, which will generate an output pulse of user-defined width.
This macrocell can also operate in a frequency detection.
This macrocell can have its active count value read via I2C. See Section 15.5.3 for further details
8.3.1 4-Bit LUT or 16-Bit CNT/DLY Block Diagram
Figure 46: 4-bit LUT0 or CNT/DLY0
CNT/DLY0 OUT
ext_CLK
DLY_in/CNT_Reset
LUT4_0
OUT
IN0
IN1
16-bits NVM
IN2
IN3
reg <1303:1288>
CMO* <33>
CMO*<31>
To Connection
Matrix Input <39>
FSM
UP
KEEP
CMO* <32>
LUT Truth
Table
CNT
Data
S1
S0
S0
S1
Config
Data
reg <1314:1304>,
reg<1287>
CMO* <30>
DFF9
CLK
D
nSET
Q/nQ
DFF
Registers
nRST
CMO*<32>
S1
S0
0
CMO* <33>
S1
S0
0
S0
S1
S2
S3
CMO* <33>
CMO* <32>
CMO* <31>
CMO* <30>
reg <
1281:1280>
1
S1
S0
S1
S0
S1
S0
S0
S1
S0
S1
S0
S1
S0
S1
S0
S1
0
S0
S1
0
S0
S1
1
S0
S1
S0
S1
S2
S3
0
LUT/DFF Sel
To Connection
Matrix Input <47>
reg <1303> DFF or Latch Select
reg <1302> Output Select (Q or nQ)
reg <1301> DFF Initial Polarity Select
reg<1282>
reg<1284:1283>,
reg<1281:1280>
Note: CMO - Connection Matrix Output
reg <1335:1320>
S0
S1
S2
S3
0
CMO* <32>
CMO* <31>
0
reg <1286:1285>
reg <1284:1283>
reg <1281:1280>
S0
S1
CMO* <31>
reg <1286:1285>,
reg<1281:1280>


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