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SLG46824 Datasheet(PDF) 63 Page - Dialog Semiconductor

Part No. SLG46824
Description  GreenPAK Programmable Mixed Signal Matrix with In System
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Maker  DIALOG [Dialog Semiconductor]
Homepage  http://www.dialog-semiconductor.com/
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SLG46824 Datasheet(HTML) 63 Page - Dialog Semiconductor

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Datasheet
31-Jan-2018
CFR0011-120-01
Revision 2.3
63 of 152
© 2018 Dialog Semiconductor
SLG46824
GreenPAK Programmable Mixed Signal Matrix with In System
Programmability
PRELIMINARY
Each Macrocell, when programmed for a LUT function, uses a 8-bit register to define their output function:
3-Bit LUT7 is defined by reg<1351:1344>
3-Bit LUT8 is defined by reg<1383:1376>
3-Bit LUT9 is defined by reg<1423:1416>
3-Bit LUT10 is defined by reg<1455:1448>
3-Bit LUT11 is defined by reg<1495:1488>
3-Bit LUT12 is defined by reg<1527:1520>
3-Bit LUT13 is defined by reg<1567:1560>
8.2 CNT/DLY/FSM TIMING DIAGRAMS
8.2.1 Delay Mode (edge select: both, counter data: 3) CNT/DLY0 to CNT/DLY7
Figure 34: Delay Mode Timing Diagram
Delay In
OSC: force power on
(always running)
Delay Output
Asynchronous delay variable
Asynchronous delay variable
delay = period x (counter data + 1) + variable
variable is from 0 to 1 clock period
delay = period x (counter data + 1) + variable
variable is from 0 to 1 clock period
Delay In
OSC: auto power on
(powers up from delay in)
Delay Output
offset
offset
delay = offset + period x (counter data + 1)
See offset in table 3
delay = offset + period x (counter data + 1)
See offset in table 3


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