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SLG46824 Datasheet(PDF) 54 Page - Dialog Semiconductor

Part No. SLG46824
Description  GreenPAK Programmable Mixed Signal Matrix with In System
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Maker  DIALOG [Dialog Semiconductor]
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SLG46824 Datasheet(HTML) 54 Page - Dialog Semiconductor

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Datasheet
31-Jan-2018
CFR0011-120-01
Revision 2.3
54 of 152
© 2018 Dialog Semiconductor
SLG46824
GreenPAK Programmable Mixed Signal Matrix with In System
Programmability
PRELIMINARY
8
Multi-Function Macrocells
The SLG46824 has 8 Multi-Function macrocells that can serve more than one logic or timing function. In each case, they can
serve as a LUT, DFF with flexible settings, or as CNT/DLY with multiple modes such as One Shot, Frequency Detect, Edge Detect
etc. Also, the macrocell is capable to combine those functions: LUT/DFF connected to CNT/DLY or CNT/DLY connected to LUT/
DFF, see Figure 26.
See the list below for the functions that can be implemented in these macrocells:
Seven macrocells that can serve as 3-bit LUTs / D Flip Flops and as 8-Bit Counter / Delays
One macrocell that can serve as a 4-bit LUT / D Flip Flop and as 16-Bit Counter / Delay / FSM
Inputs/Outputs for the 8 Multi-Function macrocells are configured from the connection matrix with specific logic functions being
defined by the state of NVM bits.
When used as a LUT to implement combinatorial logic functions, the outputs of the LUTs can be configured to any user defined
function, including the following standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR).
8.1 3-BIT LUT OR 8- BIT COUNTER / DELAY MACROCELLS
There are seven macrocells that can serve as 3-bit LUTs / D Flip Flops and as 8-Bit Counter / Delays.
When used to implement LUT functions, the 3-bit LUTs each take in three input signals from the connection matrix and produce
a single output, which goes back into the connection matrix or can be connected to CNT/DLY's input.
When used to implement D Flip Flop function, the three input signals from the connection matrix go to the data (D), clock (CLK),
and Set/Reset (nRST/nSET) inputs of the Flip Flop, with the output going back to the connection matrix or to the CNT/DLY's input.
When used to implement Counter / Delays, each macrocell has a dedicated matrix input connection. For flexibility, each of these
macrocells has a large selection of internal and external clock sources, as well as the option to chain from the output of the
previous (N-1) CNT/DLY macrocell, to implement longer count / delay circuits. These macrocells can also operate in a One-Shot
mode, which will generate an output pulse of user-defined width. They can also operate in a Frequency Detection or Edge
Detection mode.
Counter/Delay macrocell has an initial value, which define its initial value after GPAK is powered up. It is possible to select initial
Low or initial High, as well as initial value defined by a Delay In signal.
For example, in case initial LOW option is used, the rising edge delay will start operation.
For timing diagrams refer to Section 8.2.
Three of eight macrocells can have their active count value read/write via I2C (CNT0, CNT2 and CNT4). In this mode, it is possible
to load count data immediately (plus two clock cycles) or after counter ends counting. See Section 15.5.3 for further details.
Figure 26: Possible Connections Inside Multi-Function Macrocell
LUT
or
DFF
CNT/DLY
LUT
or
DFF
CNT/DLY
To Connection Matrix
To Connection
Matrix
To Connection Matrix
To Connection
Matrix


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