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SLG46824 Datasheet(PDF) 50 Page - Dialog Semiconductor

Part No. SLG46824
Description  GreenPAK Programmable Mixed Signal Matrix with In System
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Maker  DIALOG [Dialog Semiconductor]
Homepage  http://www.dialog-semiconductor.com/
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SLG46824 Datasheet(HTML) 50 Page - Dialog Semiconductor

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Datasheet
31-Jan-2018
CFR0011-120-01
Revision 2.3
50 of 152
© 2018 Dialog Semiconductor
SLG46824
GreenPAK Programmable Mixed Signal Matrix with In System
Programmability
PRELIMINARY
The overall time of the delay is based on the clock used in the SLG46824 design. Each DFF cell has a time delay of the inverse
of the clock time (either external clock or the internal Oscillator within the SLG46824). The sum of the number of DFF cells used
will be the total time delay of the Pipe Delay logic cell. OUT1 Output can be inverted (as selected by reg <1256>).
In the Ripple Counter mode, there are 3 options for setting, which use 7 bits. There are 3 bits to set nSET value (SV) in range
from 0 to 7. It is a value, which will be set into the Ripple Counter outputs when nSET input goes LOW. End value (EV) will use
3 bits for setting outputs code, which will be last code in the cycle. After reaching the EV, the Ripple Counter goes to the first code
by the rising edge on CLK input. The Functionality mode option uses 1 bit. This setting defines how exactly Ripple Counter will
operate.
The user can select one of the functionality modes by register: RANGE or FULL. If the RANGE option is selected, the count starts
from SV. If UP input is LOW the count goes down: SV->EV->EV-1 to SV+1->SV etc (if SV is smaller than EV) or SV->SV-1 to
EV+1->EV->SV (if SV is bigger than EV). If UP input is HIGH, count starts from SV up to EV etc.
In the FULL range configuration the Ripple Counter functions as follows. If UP input is LOW, the count starts from SV and goes
down to 0. Then current counter value jumps to EV and goes down to 0 etc.
If UP input is HIGH, count goes up starting from SV. Then current counter value jumps to 0 and counts up to EV etc. see Ripple
counter functionality example in Figure 25.
Every step is executed by the rising edge on CLK input.


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