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SLG46824 Datasheet(PDF) 49 Page - Dialog Semiconductor

Part No. SLG46824
Description  GreenPAK Programmable Mixed Signal Matrix with In System
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Maker  DIALOG [Dialog Semiconductor]
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SLG46824 Datasheet(HTML) 49 Page - Dialog Semiconductor

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Datasheet
31-Jan-2018
CFR0011-120-01
Revision 2.3
49 of 152
© 2018 Dialog Semiconductor
SLG46824
GreenPAK Programmable Mixed Signal Matrix with In System
Programmability
PRELIMINARY
7.4 3-BIT LUT OR PIPE DELAY / RIPPLE COUNTER MACROCELL
There is one macrocell that can serve as either a 3-bit LUT or as a Pipe Delay / Ripple Counter.
When used to implement LUT functions, the 3-bit LUT takes in three input signals from the connection matrix and produces a
single output, which goes back into the connection matrix.
When used as a pipe delay, there are three inputs signals from the matrix, Input (IN), Clock (CLK) and Reset (nRST). The pipe
delay cell is built from 16 D Flip-Flop logic cells that provide the three delay options, two of which are user selectable. The DFF
cells are tied in series where the output (Q) of each delay cell goes to the next DFF cell input (IN). Both of the two outputs (OUT0
and OUT1) provide user selectable options for 1 – 16 stages of delay. There are delay output points for each set of the OUT0 and
OUT1 outputs to a 4-input mux that is controlled by reg <1251:1248> for OUT0 and reg <1255:1252> for OUT1. The 4-input mux
is used to control the selection of the amount of delay.
Figure 23: DFF Polarity Operations with nSet
VDD
Data
Clock
POR
nSet (Case 1)
Q with nSet (Case 2)
Initial Polarity: High
Initial Polarity: Low
nSet (Case 1)
Q with nSet (Case 1)
nSet (Case 2)
Q with nSet (Case 2)
Q with nSet (Case 1)
nSet (Case 2)


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