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SLG46824 Datasheet(PDF) 4 Page - Dialog Semiconductor

Part No. SLG46824
Description  GreenPAK Programmable Mixed Signal Matrix with In System
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Maker  DIALOG [Dialog Semiconductor]
Homepage  http://www.dialog-semiconductor.com/
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SLG46824 Datasheet(HTML) 4 Page - Dialog Semiconductor

 
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Datasheet
31-Jan-2018
CFR0011-120-01
Revision 2.3
4 of 152
© 2018 Dialog Semiconductor
SLG46824
GreenPAK Programmable Mixed Signal Matrix with In System
Programmability
PRELIMINARY
Figures
Figure 1: Block Diagram ............................................................................................................................................................6
Figure 2: Steps to Create a Custom GreenPAK Device ..........................................................................................................22
Figure 3: IO with I2C Mode IO Structure Diagram ..................................................................................................................24
Figure 4: Matrix OE IO Structure Diagram ..............................................................................................................................25
Figure 5: GPIO Register OE IO Structure Diagram .................................................................................................................26
Figure 6: GPIO Register OE IO Structure Diagram .................................................................................................................27
Figure 7: Connection Matrix ....................................................................................................................................................28
Figure 8: Connection Matrix Example .....................................................................................................................................28
Figure 9: 2-bit LUT0 or DFF0 ..................................................................................................................................................35
Figure 10: 2-bit LUT1 or DFF1 ................................................................................................................................................36
Figure 11: 2-bit LUT2 or DFF2 ................................................................................................................................................36
Figure 12: DFF Polarity Operations .........................................................................................................................................38
Figure 13: 2-bit LUT3 or PGEN ...............................................................................................................................................39
Figure 14: PGEN Timing Diagram ...........................................................................................................................................40
Figure 15: 3-bit LUT0 or DFF3 ................................................................................................................................................41
Figure 16: 3-bit LUT1 or DFF2 ................................................................................................................................................42
Figure 17: 3-bit LUT1 or DFF4 ................................................................................................................................................42
Figure 18: 3-bit LUT2 or DFF5 ................................................................................................................................................43
Figure 19: 3-bit LUT3 or DFF6 ................................................................................................................................................43
Figure 20: 3-bit LUT4 or DFF7 ................................................................................................................................................44
Figure 21: 3-bit LUT5 or DFF8 ................................................................................................................................................44
Figure 22: DFF Polarity Operations with nReset .....................................................................................................................47
Figure 23: DFF Polarity Operations with nSet .........................................................................................................................48
Figure 24: 3-bit LUT6 / Pipe Delay / Ripple Counter ...............................................................................................................50
Figure 25: Example: Ripple Counter Functionality ..................................................................................................................51
Figure 26: Possible Connections Inside Multi-Function Macrocell ..........................................................................................53
Figure 27: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT7/DFF10, CNT/DLY1) ..................................................54
Figure 28: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT8/DFF11, CNT/DLY2) ..................................................55
Figure 29: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT9/DFF12, CNT/DLY3) ..................................................56
Figure 30: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT10/DFF13, CNT/DLY4) ................................................57
Figure 31: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT11/DFF14, CNT/DLY5) ................................................58
Figure 32: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT12/DFF15, CNT/DLY6) ................................................59
Figure 33: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT13/DFF16, CNT/DLY7) ................................................60
Figure 34: Delay Mode Timing Diagram ..................................................................................................................................62
Figure 35: Counter Mode Timing Diagram without two DFFs Synced up ...............................................................................63
Figure 36: Counter Mode Timing Diagram with two DFFs Synced up ....................................................................................63
Figure 37: One-Shot Function Timing Diagram .......................................................................................................................64
Figure 38: Frequency Detection Mode Timing Diagram ..........................................................................................................65
Figure 39: Edge Detection Mode Timing Diagram ..................................................................................................................66
Figure 40: Delay Mode Timing Diagram ..................................................................................................................................67
Figure 41: CNT/FSM Timing Diagram (Reset Rising Edge Mode, Oscillator is Forced On, UP=0) for Counter Data = 3 ......67
Figure 42: CNT/FSM Timing Diagram (Set Rising Edge Mode, Oscillator is Forced On, UP=0) for Counter Data = 3 ..........68
Figure 43: CNT/FSM Timing Diagram (Reset Rising Edge Mode, Oscillator is Forced On, UP=1) for Counter Data = 3 ......68
Figure 44: CNT/FSM Timing Diagram (Set Rising Edge Mode, Oscillator is Forced On, UP=1) for Counter Data = 3 ..........69
Figure 45: Counter Value, Counter Data = 3 ...........................................................................................................................69
Figure 46: 4-bit LUT0 or CNT/DLY0 ........................................................................................................................................70
Figure 47: ACMP0L Block Diagram ........................................................................................................................................73
Figure 48: ACMP1L Block Diagram ........................................................................................................................................74
Figure 49: Programmable Delay .............................................................................................................................................75
Figure 50: Edge Detector Output ............................................................................................................................................75
Figure 51: Deglitch Filter / Edge Detector ...............................................................................................................................76
Figure 52: Voltage Reference Block Diagram .........................................................................................................................78
Figure 53: Oscillator0 Block Diagram ......................................................................................................................................80
Figure 54: Oscillator1 Block Diagram ......................................................................................................................................81
Figure 55: Oscillator2 Block Diagram ......................................................................................................................................82
Figure 56: Clock Scheme ........................................................................................................................................................83


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