PRELIMINARY
CY7C1471V33
CY7C1473V33
CY7C1475V33
Document #: 38-05288 Rev. *E
Page 10 of 29
Burst Write Accesses
The CY7C1471V33, CY7C1473V33, and CY7C1475V33
have an on-chip burst counter that allows the user the ability
to supply a single address and conduct up to four Write opera-
tions without reasserting the address inputs. ADV/LD must be
driven LOW in order to load the initial address, as described
in the Single Write Access section above. When ADV/LD is
driven HIGH on the subsequent clock rise, the Chip Enables
(CE1, CE2, and CE3) and WE inputs are ignored and the burst
counter is incremented. The correct BWX inputs must be
driven in each cycle of the burst write, in order to write the
correct bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE1, CE2, and CE3, must remain inactive
for the duration of tZZREC after the ZZ input returns LOW.
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Linear Burst Address Table
(MODE = GND)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min.
Max.
Unit
IDDZZ
Sleep mode standby current
ZZ > VDD – 0.2V
150
mA
tZZS
Device operation to ZZ
ZZ > VDD – 0.2V
2tCYC
ns
tZZREC
ZZ recovery time
ZZ < 0.2V
2tCYC
ns
tZZI
ZZ active to sleep current
This parameter is sampled
2tCYC
ns
tRZZI
ZZ Inactive to exit sleep current
This parameter is sampled
0
ns
Truth Table [2, 3, 4, 5, 6, 7, 8]
Operation
Address
Used
CE1 CE2 CE3 ZZ ADV/LD
WE
BWX
OE
CEN
CLK
DQ
Deselect Cycle
None
H
X
X
L
L
X
X
X
L
L->H
Tri-State
Deselect Cycle
None
X
X
H
L
L
X
X
X
L
L->H
Tri-State
Deselect Cycle
None
X
L
X
L
L
X
X
X
L
L->H
Tri-State
Continue Deselect Cycle
None
X
X
X
L
H
X
X
X
L
L->H
Tri-State
Read Cycle
(Begin Burst)
External
L
H
L
L
L
H
X
L
L
L->H Data Out (Q)
Read Cycle
(Continue Burst)
Next
X
X
X
L
H
X
X
L
L
L->H Data Out (Q)
NOP/Dummy Read
(Begin Burst)
External
L
H
L
L
L
H
X
H
L
L->H
Tri-State
Dummy Read
(Continue Burst)
Next
X
X
X
L
H
X
X
H
L
L->H
Tri-State
Write Cycle (Begin Burst)
External
L
H
L
L
L
L
L
X
L
L->H
Data In (D)
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. BWx = L signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired Byte Write
Selects are asserted, see Truth Table for details.
3. Write is defined by BWX, and WE. See Truth Table for Read/Write.
4. When a Write cycle is detected, all I/Os are tri-stated, even during Byte Writes.
5. The DQs and DQPX pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. CEN = H, inserts wait states.
7. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a read cycle DQs and DQPX = Tri-state when OE
is inactive or when the device is deselected, and DQs and DQPX = data when OE is active.
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