SLG3SY3952V datasheet(3/10 Pages) DIALOG

Part #	SLG3SY3952V

Description	1:3 Clock Buffer

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Manufacturer	DIALOG [Dialog Semiconductor]

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000-003SY3952-04

Page 3 of 10

SLG3SY3952

26 MHz Clock Output Characteristics (26M)

TA = 25 °C, VDD = 1.8 V (unless otherwise stated)

Symbol

Description

Conditions

Min

Typ

Max

Unit

FINI

Initial Frequency

5

--

50

MHz

DC

Duty Cycle

0.5 x VDD

45

50

55

%

VOH

Output Voltage HIGH

IOH = 1 mA

0.8 x

VDD

-- 2

--

V

VOL

Output Voltage LOW

IOL = -1 mA

--

-- 2

0.2 x

VDD

V

tPU

3,5

Power Up Delay (tPU,MHz)

See Note 3 & 5

--

3

5

μs

tOE

4,5

Output Enable Delay (tOE,MHz)

See Note 4 & 5

0

1.0

2.0

μs

tR

Rise Time

measured between

VOH,min and VOL,max

--

TBD

--

ns

tF

Fall Time

measured between

VOH,min and VOL,max

--

TBD

--

ns

CL

Output Load Capacitance

--

8

10

pF

Notes:

1. This parameter tracks Reference Crystal characteristics.

2. VOH = 1.0 x VDD (typ) and VOL = 0 V (typ) when driving a fully capacitive load, i.e. IOH = IOL = 0 mA.

3. This parameter is applicable when the device powers up into Active Mode (OE = VDD during power up) or transitions into Active Mode

immediately after power up. The delay time is referenced from the point where VDD ≥ VDD,min is met to the 26 MHz output being stable and

valid. If OE is left floating, tPU may be longer.

4. This parameter is applicable when the device enters Active Mode from Hibernate Mode during normal operation. The delay time is refer-

enced from the point where OE

≥ V

IH,min is met to the 26 MHz output being stable and valid.

5. Both tPU and tOE should be satisfied in order for the 26 MHz output to be stable and valid.

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