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CS4103 Datasheet(PDF) 4 Page - National Semiconductor (TI) |
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CS4103 Datasheet(HTML) 4 Page - National Semiconductor (TI) |
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4 / 24 page  www.national.com 4 Revision 1.0 Architectural Overview (Continued) 1.2 ARBITER The Arbiter includes the logic to implement all of the state machines described in clause 7, revision 2.0 of the P1394a specification except for the Port State machine. These include the state machines for bus reset, Tree-ID, Self-ID, and normal arbitration. The Arbiter monitors the received line states and controls the transmitted and repeated line states for the various types of arbitration processes. The Arbiter maintains the arbitration timer responsible for timing the various gaps and line state lengths required for P1394a operation. It also receives bus requests from the CS4210 via the Link Interface and sends the appropriate handshake signals to indicate won/lost status to the Link Interface. 1.3 REGISTER SET The Register Set implements all of the registers defined in the P1394a specification. The Register Set has interfaces to the Link Interface module for register reads and writes as well as to the Packet Processor for register reads. The Register Set also contains several National Semiconductor specific register bits implemented in the address page which are set aside for vendor specific registers and inter- faces with the Arbiter and Port State. For example, the Root hold-off bit affects the Arbiter and the Port Disabled bits affect the operation of the Port State. 1.4 PACKET PROCESSOR The Packet Processor decodes all PHY packets received by the CS4103, (from both the CS4210 and cable inter- faces) and generates all PHY response packets that the CS4103 must send autonomously. The Packet Processor also provides validity checking on PHY packets, discarding invalid packets. During bus initialization and configuration, the Packet Processor signals the reception of Self-ID pack- ets to the Arbiter. The Arbiter uses this information during the Self-ID process to increment the Node ID count. 1.5 PORT STATE The Port State contains the Port Connection State Machine described in clause 7.10.4, revision 2.0 of the P1394a specification. The Port State keeps track of the connect status and state of each port, (Disconnect, Resuming, Active, etc.). The Port State also implements the connec- tion timer used for timing various transitions within the state machine and reports certain state conditions to other mod- ules. For example, the Port State signals the Arbiter with the Active, Resume, and Suspend state of each port along with other status information. It also reports connection change information for waking the CS4103 from a low- power mode. 1.6 RECEIVER The Receiver consists of the logic responsible for the data/ strobe decoding, the serial-to-parallel converter, and the re-time FIFO. During packet reception and repeating, the re-time FIFO buffers the data to allow for frequency differ- ences between the transmitting and receiving PHYs. The CS4103 writes data into the FIFO using the recovered clock from the incoming data stream. It removes data from theFIFO using thelocal system clock. Thesizeofthe FIFO is calculated to allow the successful reception of a maxi- mum length packet with a maximum clock offset between this PHY and the Transmitter. 1.7 TRANSMITTER The Transmitter handles the parallel-to-serial conversion and data/strobe encoding operations. It can transmit data from one of three sources: the Link Interface, the on-chip Packet Processor, and the repeat path. The Arbiter controls which path is selected for each transmit operation. 1.8 TRANSCEIVER The Transceiver handles the interface to the 1394 cable. It has drivers and receivers for the cable wires, (TPA+, TPA–, TPB+, and TPB–). In addition, each Transceiver provides a TpBias output for its port. On transmit, the Transceiver gen- erates the appropriate speed signaling for 100, 200, and 400 Mbit/sec operation. The Transceiver also transmits 1, 0, and Z values on each differential pair (TPA and TPB). The Receiver detects speed signaling values and the Arbi- tration line states (1, 0, and Z). It contains separate differ- ential receivers used to interpret data and strobe during packet reception. The Transceiver logic contains TpBias detection circuitry as well as a Connect Detect circuit. The Transceiver enables the Connect Detect circuit when the Port State logic instructs the Transceiver to turn off the TpBias generation, (for example, when the port enters the Suspend state). 1.9 PHASE-LOCKED LOOP (PLL) The PLL module uses a 24.576 MHz crystal or clock input to generate all of the local clocks. These include the 49.152 MHz system clock (SCLK) as well as the 98.304 MHz, 196.698 MHz, and 393.216 MHz clocks necessary for transmitting at 100, 200, and 400 Mbit/sec. This PLL design requires no external filter components. 1.10 RELATED DOCUMENTS The following documents may be useful in understanding the terms and concepts used in this publication. • IEEE Standard 1394-1995 “IEEE Standard for a high performance serial Bus” • P1394a Draft 2.0 “P1394a Draft Standard for a High Performance Serial Bus” (supplement) |
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