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ATDS1100PC Datasheet(PDF) 1 Page - ATMEL Corporation |
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ATDS1100PC Datasheet(HTML) 1 Page - ATMEL Corporation |
1 / 8 page 1 Features • Comprehensive CPLD/PLD Design Environment • User-friendly Microsoft Windows™ Interface (Win 95, Win 98, Win NT) • Powerful Project Navigator – Utilizes Intelligent Device Fitters for Automatic Logic Synthesis and Device Resource Assignment – Allows Design Specification with Schematic Entry or the ABEL-HDL • Integrated ABEL Text Design Entry and Synthesis – Friendly Windows-based User Interface is Easy to Learn and Use – ABEL-HDL Design Entry Provides Detailed Support for Programmable Logic Devices – Full Hierarchical Support Makes Large Designs Easier to Manage; Large All-behavioral Designs can be Created without Drawing any Schematics • Integrated Verilog™ Timing Simulator (Optional) – Fast, Functional Simulation is Performed Directly from the Schematic or Behavioral Source File, Providing Quick Feedback on Logic Errors as the Design is Entered – Full Timing Simulation with Delay-annotated Models Provides Comprehensive Support for Timing Problems in Routed Devices – Logic-analyzer-like Waveform Viewer Provides Flexible Results Viewing, and Updates Every Time you Single-step the Simulator – Cross-probing Capabilities between the Schematic and Waveform Viewer Tie Simulation Results Directly Back to the Source Design, Making Results Easier to Interpret – Interactive Debugging Provides Force/Preset/Monitor Access to all of the Design’s Signals, for Fast and Easy, On-the-fly Changes – Industry-standard Verilog HDL Simulation Language Ensures Timely Support for New Device Architectures • IEEE 1076 VHDL Synthesis and Simulation (Optional) Description Atmel-Synario is an integrated CPLD/PLD design tool. It supports all proprietary, and JEDEC standard devices offered by Atmel. The usual CAE tool capability is combined with CPLD specific functionality. A tightly integrated Windows environment gives the user a friendly, and powerful interface. The system combines schematic and behav- ioral entry methods. Functional and timing simulation are also supported. An intelligent design manager, supervises file manipulation and controls the design flow. This function allows a user to move quickly from one design to another and evaluate different implementations for an optimal solution. Atmel-Synario CPLD/PLD Design Software ATDS1100PC ATDS1120PC ATDS1130PC ATDS1140PC Rev. 0714C–09/99 |
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