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DRA74XP Datasheet(PDF) 5 Page - Texas Instruments |
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DRA74XP Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 481 page  5 DRA75P, DRA74P www.ti.com SPRS989D – DECEMBER 2016 – REVISED DECEMBER 2017 Submit Documentation Feedback Product Folder Links: DRA75P DRA74P Revision History Copyright © 2016–2017, Texas Instruments Incorporated 2 Revision History Changes from September 26, 2017 to December 15, 2017 (from C Revision (September 2017) to D Revision) Page • Added Secure Boot feature in Section 1.1, Section 1.3 and Figure 1-1 ....................................................... 1 • Updated Table 3-1 to identify the ISS feature overall as “optional”, along with a footnote (2) ............................. 6 • Added vpp ball information to Table 4-1 Pin Attributes, Table 4-32 Power Supply Signal Descriptions, and Table 4-34 Unused Balls Specific Connection Requirements. ............................................................... 13 • Removed restriction on VOUT to operate in 1.8 V only onto balls mapped to the vddshv6 supply rail in Table 4-1 and Table 4-3 as it is not applicable to this device ............................................................................. 80 • Added tie-off guidance for unused dqs, dqsn and I2C2 pins to Table 4-34 ................................................ 138 • Added new VPP Specification section about One-Time Programmable (OTP) eFuses ................................. 175 • Updated Package Thermal Characteristics section ........................................................................... 176 • Removed restriction on VOUT to operate in 1.8 V only onto balls mapped to the vddshv6 supply rail in VOUT IOSET Table 5-50 ................................................................................................................. 228 • Added CAN delay time receive and transmit parameters in relation to the shift registers .............................. 301 • Added Secure Boot feature in Section 6.1 and Figure 6-1 ................................................................... 346 • Updated maximum ISP throughput in Section 6.5 ............................................................................ 355 • Power Integrity Updates: Section 7.3 is updated to align with new PDN power integrity recommendations and provided EVM PCB PDN PI performance & Dcap scheme implementation results. ..................................... 402 • Added High Security suffix “S” to Table 8-1 Nomenclature Description ................................................... 475 • Added ISS designator "I" to Figure 8-1 and Table 8-1 ........................................................................ 475 |
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