DAC60508MRTER datasheet(7/53 Pages) TI1

Part #	DAC60508MRTER

Description	Octal, 16-, 14-, 12-Bit, SPI, Voltage Output DAC with Internal Reference

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Manufacturer	TI1 [Texas Instruments]

Direct Link	http://www.ti.com

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DAC80508Z, DAC70508Z, DAC60508Z, DAC80508M, DAC70508M, DAC60508M

www.ti.com

SLASEL1B – JUNE 2017 – REVISED JANUARY 2018

Product Folder Links: DAC80508Z DAC70508Z DAC60508Z DAC80508M DAC70508M DAC60508M

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Electrical Characteristics (continued)

All minimum and maximum specifications at VDD= 2.7 V to 5.5 V, VIO = 1.7 V to 5.5 V, VREFIN = 1.25 V to 5.5 V, RLOAD = 2 kΩ

to GND, CLOAD = 200 pF to GND, digital inputs at VIO or GND, TA = –40°C to 125°C (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

(2)

Temporary overload condition protection. Junction temperature can be exceeded during current limit. Operation above the specified

maximum junction temperature may impair device reliability.

(3)

Specified by design and characterization. Not tested during production.

(4)

Time to exit DAC power-down mode. Measured from CS rising edge to 90% of DAC final value.

OUTPUT CHARACTERISTICS

Voltage range

Gain = 2 (BUFF-GAIN = 1, REF-DIV = 0)

0

2 × VREF

V

Gain = 1 (BUFF-GAIN = 1, REF-DIV = 1)

0

VREF

Gain = ½ (BUFF-GAIN = 0, REF-DIV = 1)

0

½ × VREF

Output voltage headroom

to GND or VDD (unloaded)

0.004

V

to GND or VDD (-5 mA ≤ IOUT ≤ 5 mA)

0.15

to GND or VDD (-10 mA ≤ IOUT ≤ 10 mA)

0.3

to GND or VDD (-20 mA ≤ IOUT ≤ 20 mA)

0.5

Short circuit current

(2)

DAC code = full scale. Output shorted to GND

35

mA

DAC code = zero scale. Output shorted to VDD

30

Load regulation

DAC code = midscale, -10 mA

≤ IOUT ≤ 10 mA

85

µV/mA

Maximum capacitive load

(3)

RLOAD = ∞

0

2

nF

RLOAD = 2 kΩ

0

10

DC output impedance

DAC code = midscale

0.085

Ω

DAC output at GND or VDD

15

DYNAMIC PERFORMANCE

Output voltage settling time

¼ to ¾ scale and ¾ to ¼ scale settling time to ±2

LSB, VDD = 5.5 V, VREFIN = 2.5 V, Gain = 2

5

µs

Slew rate

VDD = 5.5 V, VREFIN = 2.5 V, Gain = 2

1.8

V/µs

Power-up time

DACx-PWDWN 1 to 0 transition. DAC code = full

scale. VDD = 5.5 V, VREFIN = 2.5 V, Gain = 2

(4)

12

µs

Power-up glitch magnitude

DAC code = zero scale. VDD = 5.5 V, VREFIN = 2.5 V,

Gain = 2. CLOAD = 50 pF

25

mV

Output noise

0.1 Hz to 10 Hz, DAC code = midscale, VDD = 5.5 V,

VREFIN = 2.5 V, Gain = 2

14

µVpp

Output noise density

1 kHz, DAC code = midscale, VDD = 5.5 V, VREFIN =

2.5 V, Gain = 2

78

nV/

√Hz

10 kHz, DAC code = midscale, VDD = 5.5 V, VREFIN =

2.5 V, Gain = 2

74

1 kHz, DAC code = full scale, VDD = 5.5 V, VREFIN =

2.5 V, Gain = 1

55

10 kHz, DAC code = full scale, VDD = 5.5 V, VREFIN =

2.5 V, Gain = 1

50

AC PSRR

DAC code = midscale, frequency = 60 Hz, amplitude

= 200 mVPP superimposed on VDD

85

dB

DC PSRR

DAC code = midscale, VDD = 5 V ± 10%

10

µV/V

Code change glitch impulse

1 LSB change around major carrier

4

nV-s

Channel to Channel AC crosstalk

DAC code = midscale. Code 32 to full-scale swing on

adjacent channel

0.2

nV-s

Channel to Channel DC crosstalk

Measured channel at midscale. Adjacent channel at

full scale.

10

µV

Measured channel at midscale. All other channels at

full scale.

80

Digital feedthrough

DAC code = midscale. fSCLK = 1 MHz, SDO disabled

0.1

nV-s

EXTERNAL REFERENCE INPUT

Reference input current

VREFIN = 2.5 V

25

µA

Reference input impedance

100

kΩ

Reference input capacitance

5

pF

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