CDCM6208V2RGZT datasheet(69/92 Pages) TI1

Part #	CDCM6208V2RGZT

Description	2:8 Clock Generator, Jitter Cleaner With Fractional Dividers

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Manufacturer	TI1 [Texas Instruments]

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SEC_REF

VCO

=

M

(N × PS_A)

f

PRI_REF

VCO

=

(M × R)

(N × PS_A)

f

A

Ref -14.1 dBm

At t

5 dB

*

1

R M

C L R W R

RBW 30 kHz

VBW 300 kHz

SWT 1 s

N O R

*

Center 245.76 MHz

Span 25.5 MHz

2.55 MHz/

PRN

- 1 1 0

- 1 0 0

- 9 0

- 8 0

- 7 0

- 6 0

- 5 0

- 4 0

- 3 0

-20

Tx Channe l

W-CDMA 3GPP FWD

Bandwi dth

3.84 MHz

P o w e r

- 9 . 3 9

d B m

Ad j acent Channe l

Bandwi dth

3.84 MHz

L o w e r

- 7 2 . 8 1

d B

Spac i ng

5 MHz

U p p e r

- 7 2 . 4 0

d B

Al ternate Channe l

Bandwi dth

3.84 MHz

L o w e r

- 7 7 . 7 9

d B

Spac i ng

10 MHz

U p p e r

- 7 8 . 3 1

d B

A

Ref -14.1 dBm

At t

5 dB

*

1

R M

C L R W R

RBW 30 kHz

VBW 300 kHz

SWT 1 s

N O R

*

Center 245.76 MHz

Span 25.5 MHz

2.55 MHz/

PRN

- 1 1 0

- 1 0 0

- 9 0

- 8 0

- 7 0

- 6 0

- 5 0

- 4 0

- 3 0

-20

Tx Channe l

W-CDMA 3GPP FWD

Bandwi dth

3.84 MHz

P o w e r

- 9 . 4 0

d B m

Ad j acent Channe l

Bandwi dth

3.84 MHz

L o w e r

- 7 3 . 1 2

d B

Spac i ng

5 MHz

U p p e r

- 7 3 . 0 6

d B

Al ternate Channe l

Bandwi dth

3.84 MHz

L o w e r

- 7 9 . 2 2

d B

Spac i ng

10 MHz

U p p e r

- 7 9 . 1 9

d B

245.76MHz DAC

driven from ³LGHDO VRXUFH´

(Wenzel oscillator buffered by HP8133A)

245.76MHz DAC

driven from CDCM6208

(no performance degradation observed)

69

CDCM6208

www.ti.com

SCAS931G – MAY 2012 – REVISED JANUARY 2018

Product Folder Links: CDCM6208

Submit Documentation Feedback

Observation: Up to an IF = 100 MHz, the ADC performance when driven by the CDCM6208 (Figure 53) is

similar to when the ADC is driven by an expensive lab signal generator with additional passive source filtering

(Figure 52).

Conclusion: Therefore, the CDCM6208 is usable for applications up to 100 MHz IF. For IF above 100 MHz, the

SNR starts degrading in our experiments. Measurements were conducted with ADC connected to Y0 and other

outputs running at different integer frequencies.

NOTE

For crosstalk, TI highly recommends configuring both pre-dividers identically, otherwise

the SFDR and SNR suffer due to crosstalk between the two pre-divider frequencies.

Figure 54. DAC Driven by Lab Source and CDCM6208 in Comparison (Performance Identical)

Observation/Conclusion: The DAC performance was not degraded at all by the CDCM6208 compared to

driving the DAC with a perfect lab source. Therefore, the CDCM6208 provides sufficient low noise to drive a

245.76 MHz DAC.

9.2.2.3 Configuring the PLL

The CDCM6208 allows configuring the PLL to accommodate various input and output frequencies either through

an I2C or SPI programming interface or in the absence of programming, the PLL can be configured through

control pins. The PLL can be configured by setting the Smart Input MUX, Reference Divider, PLL Loop Filter,

Feedback Divider, Prescaler Divider, and Output Dividers.

For the PLL to operate in closed-loop mode, the following condition in Equation 1 has to be met when using

primary input for the reference clock, and the condition in Equation 2 has to be met when using secondary input

for the reference clock.

(1)

(2)

In Equation 1 and Equation 2, ƒPRI_REF is the reference input frequency on the primary input and ƒSEC_REF is the

reference input frequency on the secondary input, R is the reference divider, M is the input divider, N is the

feedback divider, and PS_A the prescaler divider A.

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CDCM6208V2RGZT Datasheet(PDF) 69 Page - Texas Instruments

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