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CDCM6208V2RGZT Datasheet(PDF) 65 Page - Texas Instruments |
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CDCM6208V2RGZT Datasheet(HTML) 65 Page - Texas Instruments |
65 / 92 page CDCM6208 Synthesizer Mode TMS320TCI6616/18 DSP AIF ALT CORE SRIO PCIe Packet Accel DR Base Band DSP Clocking Pico Cell Clocking DPLL CDCM6208 APLL GPS receiver IEEE1588 timing extract Ethernet SyncE Et he rne t Timing 1pps 1pps Core Packet network FBADC RXADC TXDAC RF LO RF LO 65 CDCM6208 www.ti.com SCAS931G – MAY 2012 – REVISED JANUARY 2018 Product Folder Links: CDCM6208 Submit Documentation Feedback Copyright © 2012–2018, Texas Instruments Incorporated 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The CDCM6208 is a highly integrated clock generator and jitter cleaner. The CDCM6208 derives its output clocks from an on-chip oscillator which can be buffered through integer or fractional output dividers. 9.2 Typical Applications Figure 48. Typical Application Circuit Figure 49. Typical Application Circuit 9.2.1 Design Requirements The most jitter sensitive application besides driving A-to-D converters are systems deploying a serial link using Serializer and De-serializer implementation (for example, a 10 GigEthernet). Fully estimating the clock jitter impact on the link budget requires an understanding of the transmit PLL bandwidth and the receiver CDR bandwidth. 9.2.2 Detailed Design Procedures 9.2.2.1 Jitter Considerations in SERDES Systems As shown in Figure 50, the bandwidth of TX and RX is the frequency range in which clock jitter adds without any attenuation to the jitter budget of the link. Outside of these frequencies, the SERDES link will attenuate clock jitter with a 20 dB/dec or even steeper roll-off. |
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