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CDCM6208V2RGZT Datasheet(PDF) 6 Page - Texas Instruments

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Part # CDCM6208V2RGZT
Description  2:8 Clock Generator, Jitter Cleaner With Fractional Dividers
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

CDCM6208V2RGZT Datasheet(HTML) 6 Page - Texas Instruments

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6
CDCM6208
SCAS931G – MAY 2012 – REVISED JANUARY 2018
www.ti.com
Product Folder Links: CDCM6208
Submit Documentation Feedback
Copyright © 2012–2018, Texas Instruments Incorporated
Pin Functions (continued)
PIN
I/O
TYPE
DESCRIPTION
NAME
NO.
(2)
Note: the device cannot be programmed in I2C while RESETN is held low.
RESETN/PWR
44
Input
LVCMOS
with 50-kΩ pullup
In SPI/I2C programming mode, external RESETN signal (active low).
RESETN = V IL: device in reset (registers values are retained)
RESETN = V IH: device active. The device can be programmed
through SPI while RESETN is held low (this is useful to avoid any
false output frequencies at power up). (2)
In Pin mode this pin controls device core and I/O supply voltage
setting. 0 = 1.8 V, 1 = 2.5/3.3 V for the device core and I/O power
supply voltage. In pin mode, it is not possible to mix and match the
supplies. All supplies should either be 1.8 V or 2.5/3.3 V.
REG_CAP
40
Output
Analog
Regulator Capacitor; connect a 10-µF cap with ESR below 1 Ω to
GND at frequencies above 100 kHz
PDN
43
Input
LVCMOS
with 50-kΩ pullup
Power Down Active low. When PDN = VIH is normal operation.
When PDN = VIL, the device is disabled and current consumption
minimized. Exiting power down resets the entire device and defaults
all registers. It is recommended to connect a capacitor to GND to
hold the device in power-down until the digital and PLL related
power supplies are stable. See section on power down in the
application section.
SYNCN
42
Input
LVCMOS
with 50-kΩ pullup
Active low. Device outputs are synchronized on a low-to-high
transition on the SYNCN pin. SYNCN held low disables all outputs.
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6 Specifications
6.1 Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VDD_PRI, VDD_SEC,
VDD_Yx_Yy,
VDD_PLL[2:1], DVDD
Supply voltage
–0.5
4.6
V
VIN
Input voltage for CMOS control inputs
–0.5
4.6
AND
V DVDD+ 0.5
V
Input voltage for PRI/SEC inputs
4.6
AND
VVDDPRI.SEC+
0.5
V
VOUT
Output voltage
–0.5
VYxYy+ 0.5
V
IIN
Input current
20
mA
IOUT
Output current
50
mA
TJ
Junction temperature
125
°C
Tstg
Storage temperature
–65
150
°C
(1)
Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges in
to the device.
(2)
Level listed above is the passing level per ANSI/ESDA/JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM allows safe
manufacturing with a standard ESD control process.
(3)
Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250-V CDM allows safe
manufacturing with a standard ESD control process.
6.2 ESD Ratings
VALUE
UNIT
VESD
(1)
Electrostatic discharge
Human Body Model (HBM) ESD Stress Voltage (2)
±2000
V
Charged Device Model (CDM) ESD Stress Voltage(3)
±500


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