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CDCM6208V2RGZT Datasheet(PDF) 5 Page - Texas Instruments |
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CDCM6208V2RGZT Datasheet(HTML) 5 Page - Texas Instruments |
5 / 92 page ![]() 5 CDCM6208 www.ti.com SCAS931G – MAY 2012 – REVISED JANUARY 2018 Product Folder Links: CDCM6208 Submit Documentation Feedback Copyright © 2012–2018, Texas Instruments Incorporated Pin Functions (continued) PIN I/O TYPE DESCRIPTION NAME NO. VDD_Y0_Y1 (2 pins) 13, 18 PWR Analog Supply pin for outputs 0, 1 to set between 1.8 V, 2.5 V, or 3.3 V Y2_P 20 Output Universal Output 2 Positive Pin Y2_N 21 Output Universal Output 2 Negative Pin Y3_P 23 Output Universal Output 3 Positive Pin Y3_N 22 Output Universal Output 3 Negative Pin VDD_Y2_Y3 (2 pins) 19, 24 PWR Analog Supply pin for outputs 2, 3 to set between 1.8 V, 2.5 V, or 3.3 V Y4_P 26 Output Universal Output 4 Positive Pin Y4_N 25 Output Universal Output 4 Negative Pin VDD_Y4 27 PWR Analog Supply pin for output 4 to set between 1.8 V, 2.5 V, or 3.3 V Y5_P 29 Output Universal Output 5 Positive Pin Y5_N 28 Output Universal Output 5 Negative Pin VDD_Y5 30 PWR Analog Supply pin for output 5 to set between 1.8 V, 2.5 V, or 3.3 V Y6_P 32 Output Universal Output 6 Positive Pin Y6_N 33 Output Universal Output 6 Negative Pin VDD_Y6 31 PWR Analog Supply pin for output 6 to set between 1.8 V, 2.5 V, or 3.3 V Y7_P 35 Output Universal Output 7 Positive Pin Y7_N 36 Output Universal Output 7 Negative Pin VDD_Y7 34 PWR Analog Supply pin for output 7 to set between 1.8 V, 2.5 V, or 3.3 V VDD_VCO 39 PWR Analog Analog power supply for PLL/VCO; This pin is sensitive to power supply noise; The supply of this pin and the VDD_PLL2 supply pin can be combined as they are both analog and sensitive supplies; VDD_PLL1 37 PWR Analog Analog Power Supply Connections VDD_PLL2 38 PWR Analog Analog Power Supply Connections; This pin is sensitive to power supply noise; The supply of VDD_PLL2 and VDD_VCO can be combined as these pins are both power-sensitive, analog supply pins DVDD 48 PWR Analog Digital Power Supply Connections; This is also the reference supply voltage for all control inputs and must match the expected input signal swing of control inputs. GND PAD PWR Analog Power Supply Ground and Thermal Pad STATUS0 46 Output LVCMOS Status pin 0 (see Table 12 for details) STATUS1/PIN0 45 Output and Input LVCMOS no pull resistor STATUS1: Status pin in SPI/I2C modes. For details, see Table 10 for pin modes and Table 12 for status mode. PIN0: Control pin 0 in pin mode. SI_MODE1 47 Input LVCMOS with 50-kΩ pullup Serial Interface Mode or Pin mode selection. SI_MODE[1:0]=00: SPI mode; SI_MODE[1:0]=01: I2C mode; SI_MODE[1:0]=10: Pin Mode (No serial programming); SI_MODE[1:0]=11: RESERVED SI_MODE0 1 LVCMOS with 50-kΩ pulldown SDI/SDA/PIN1 2 I/O LVCMOS in Open drain out LVCMOS in no pull resistor SDI: SPI Serial Data Input SDA: I2C Serial Data (Read/Write bidirectional), open-drain output; requires a pullup resistor in I2C mode; PIN1: Control pin 1 in pin mode SDO/AD0/PIN2 3 Output/Input LVCMOS out LVCMOS in LVCMOS in no pull resistor SDO: SPI Serial Data AD0: I2C Address Offset Bit 0 input; PIN2: Control pin 2 in pin mode SCS/AD1/PIN 3 4 Input LVCMOS no pull resistor SCS: SPI Latch EnableAD1: I2C Address Offset Bit 1 input; PIN3: Control pin 3 in pin mode SCL/PIN4 5 Input LVCMOS no pull resistor SCL: SPI/I2C ClockPIN4: Control pin 4 in pin mode |
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