Electronic Components Datasheet Search |
|
CDCM6208V1HRGZR Datasheet(PDF) 72 Page - Texas Instruments |
|
|
CDCM6208V1HRGZR Datasheet(HTML) 72 Page - Texas Instruments |
72 / 92 page ÷ 1, 2 or 3 Pre-Scaler output clock 398-800MHz Limit: 200-400MHz ÷ 4, 5 or 6 VCO 2.39-2.55GHz 2.94-3.13GHz Pre-Scaler PS_A or PS_B FracDiv Pre Divider Reg 9.12:10 Reg 12.12:10 Reg 15.12:10 Reg 18.12:10 ÷ 1 to 256 Reg 10.11:4 Reg 13.11:4 Reg 16.11:4 Reg 19.11:4 Integer Divider Reg 3.4:0 .xxx Reg 10.3:0 + Reg 11 Reg 13.3:0 + Reg 14 Reg 16.3:0 + Reg 17 Reg 19.3:0 + Reg 20 Fractional Divider (simplified) Fractional division 72 CDCM6208 SCAS931G – MAY 2012 – REVISED JANUARY 2018 www.ti.com Product Folder Links: CDCM6208 Submit Documentation Feedback Copyright © 2012–2018, Texas Instruments Incorporated 9.2.2.8 Fractional Output Divider (FOD) The CDCM6208 incorporates a fractional output divider on Y[7:4], allowing these outputs to run at non-integer output divide ratios of the PLL frequencies. This feature is useful when systems require different, unrelated frequencies. The fractional output divider architecture is shown in Figure 56. Figure 56. Fractional Output Divider Principle Architecture (Simplified Graphic, not Showing Output Divider Bypass Options) The fractional output divider requires an input frequency between 400 MHz and 800 MHz, and outputs any frequency equal or less than 400 MHz (the minimum fractional output divider setting is 2). The fractional divider block has a first stage integer pre-divider followed by a fractional sigma-delta output divider block that is deep enough such as to generate any output frequency in the range of 0.78 MHz to 400 MHz from any input frequency in the range of 400 MHz to 800 MHz with a worst case frequency accuracy of no more than ±1ppm. The fractional values available are all possible 20-b representations of fractions within the following range: • 1.0 ≤ ƒracDIV ≤ 1.9375 • 2.0 ≤ ƒracDIV ≤ 3.875 • 4.0 ≤ ƒracDIV ≤ 5.875 • x.0 ≤ ƒracDIV ≤ (x + 1) + 0.875 with x being all even numbers from x = 2, 4, 6, 8, 10, ...., 254 • 254.0 ≤ ƒracDIV ≤ 255.875 • 256.0 ≤ ƒracDIV ≤ 256.99999 The CDCM6208 user GUI comprehends the fractional divider limitations; therefore, using the GUI to comprehend frequency planning is recommended. The fractional divider output jitter is a function of fractional divider input frequency and furthermore depends on which bits are exercised within the fractional divider. Exercising only MSB or LSB bits provides better jitter than exercising bits near the center of the fractional divider. Jitter data are provided in this document, and vary from 50 ps-pp to 200 ps-pp, when the device is operated as a frequency synthesizer with high PLL bandwidths (approximately 100 kHz to 400 kHz). When the device is operated as a jitter cleaner with low PLL bandwidths (< 1 kHz), its additive total jitter increases by as much as 30 ps-pp. The fractional divider can be used in integer mode. However, if only an integer divide ratio is needed, it is important to disable the corresponding fractional divider enable bit, which engages the higher performing integer divider. 9.2.2.9 Output Synchronization Both types of output dividers can be synchronized using the SYNCN signal. For the CDCM6208, this signal comes from the SYNCN pin or the soft SYNCN register bit R3.5. The most common way to execute the output synchronization is to toggle the SYNCN pin. When SYNC is asserted (VSYNCN ≤ VIL), all outputs are disabled (high-impedance) and the output dividers are reset. When SYNC is de-asserted (VSYNCN ≥ VIH), the device first internally latches the signal, then retimes the signal with the pre-scaler, and finally turns all outputs on simultaneously. The first rising edge of the outputs is therefore approximately 15 ns to 20 ns delayed from the SYNC pin assertion. For one particular device configuration, the uncertainty of the delay is ±1 PS_A clock cycles. For one particular device and one particular configuration, the delay uncertainty is one PS_A clock cycle. |
Similar Part No. - CDCM6208V1HRGZR |
|
Similar Description - CDCM6208V1HRGZR |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |