CDCM6208_18 datasheet(78/92 Pages) TI1

Part #	CDCM6208

Description	2:8 Clock Generator, Jitter Cleaner With Fractional Dividers

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Manufacturer	TI1 [Texas Instruments]

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78 / 92 page

Frequency (Hz)

2.9 ps

-50

10M

10K

100

1000

100k

1M

9.2 ps

0.92 ps

-60

0.29 ps

-70

-100

-80

-90

0.092 ps

-65

-55

-75

-85

-95

78

CDCM6208

SCAS931G – MAY 2012 – REVISED JANUARY 2018

www.ti.com

Product Folder Links: CDCM6208

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10.3 Power Down

When the PDN pin = 0, the device enters a complete power down mode with a current consumption of no more

than 1 mA from the entire device. Exiting power down resets the entire device and defaults all registers. It is

recommended to connect a capacitor between the PDN pin and GND to implement a RC time delay and ensure

the digital and PLL related power supplies are stable before the device calibration sequences is initiated. Refer to

Power Rail Sequencing, Power Supply Ramp Rate, and Mixing Supply Domains for more details.

10.4 Power Supply Ripple Rejection (PSRR) versus Ripple Frequency

Many system designs become increasingly more sensitive to power supply noise rejection. To simplify design

and cost, the CDCM6208 has built-in internal voltage regulation, which improves the power supply noise

rejection over designs with no regulators. As a result, the following output rejection is achieved:

Figure 63. PSRR (in dBc and DJ [ps]) Over Frequency [Hz] and Output Signal Format

fOUT = 122.88 MHz

VDD Supply Noise = 100 mVpp

The DJ due to PSRR can be estimated using Equation 4:

(4)

Example: Therefore, if 100 mV noise with a frequency of 10 kHz were observed at the output supply, the

according output jitter for a 122.88-MHz output signal with LVDS signaling could be estimated with DJ = 0.7 ps.

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CDCM6208 Datasheet(PDF) 78 Page - Texas Instruments

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