SCAS931G – MAY 2012 – REVISED JANUARY 2018
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For fast power up ramps under 50 ms and when all supply pins are driven from the same power supply source, PDN can be left floating.
For slower power-up ramps or if supply pins are sequenced with uncertain time delays, PDN needs to be held low until DVDD,
VDD_PLLx, and VDD_PRI/SEC reach at least 1.45-V supply voltage. See application section on mixing power supplies and particularly
Figure 59 for details.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Output supply voltage
Core analog supply voltage
Core digital supply voltage
Reference input supply voltage
VDD power-up ramp time (0 to 3.3 V) PDN left open,
all VDD tight together PDN low-high is delayed (1)
50 < tPDN
SDA and SCL in I2C Mode (SI_MODE[1:0] = 01)
DVDD = 1.8 V
DVDD = 3.3 V
High-level input voltage
0.7 × DVDD
Low-level input voltage
0.3 × DVDD
Total capacitive load for each bus line
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report.
The package thermal resistance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board).
Connected to GND with 36 thermal vias (0.3-mm diameter).
θJB (junction to board) is used for the VQFN package, the main heat flow is from the junction to the GND pad of the VQFN.
6.4 Thermal Information, Airflow = 0 LFM
(1) (2) (3) (4)
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance