CDCM6208_18 datasheet(2/92 Pages) TI1 | 2:8 Clock Generator, Jitter Cleaner With Fractional Dividers

Part No.	CDCM6208

Description	2:8 Clock Generator, Jitter Cleaner With Fractional Dividers

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Manufacturer	TI1 [Texas Instruments]

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CDCM6208

SCAS931G – MAY 2012 – REVISED JANUARY 2018

www.ti.com

Product Folder Links: CDCM6208

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Table of Contents

1

Features .................................................................. 1

2

Applications ........................................................... 1

3

Description ............................................................. 1

4

Revision History..................................................... 2

5

Pin Configuration and Functions ......................... 4

6

Specifications......................................................... 6

6.1

Absolute Maximum Ratings ...................................... 6

6.2

ESD Ratings.............................................................. 6

6.3

Recommended Operating Conditions ....................... 7

6.4

Thermal Information, Airflow = 0 LFM....................... 7

6.5

Thermal Information, Airflow = 150 LFM................... 8

6.6

Thermal Information, Airflow = 250 LFM................... 8

6.7

Thermal Information, Airflow = 500 LFM................... 8

6.8

Single-Ended Input Characteristics (SI_MODE[1:0],

SDI/SDA/PIN1, SCL/PIN4, SDO/ADD0/PIN2,

SCS/ADD1/PIN3, STATUS1/PIN0, RESETN/PWR,

PDN, SYNCN, REF_SEL).......................................... 9

6.9

Single-Ended Input Characteristics (PRI_REF,

SEC_REF) ................................................................. 9

6.10

Differential Input Characteristics (PRI_REF,

SEC_REF) ............................................................... 10

6.11

Crystal Input Characteristics (SEC_REF) ............ 10

6.12

Single-Ended Output Characteristics (STATUS1,

STATUS0, SDO, SDA) ............................................ 11

6.13

PLL Characteristics .............................................. 11

6.14

LVCMOS Output Characteristics ......................... 12

6.15

LVPECL (High-Swing CML) Output

Characteristics ......................................................... 13

6.16

CML Output Characteristics................................. 13

6.17

LVDS (Low-Power CML) Output Characteristics . 14

6.18

HCSL Output Characteristics............................... 14

6.19

Output Skew and Sync to Output Propagation Delay

Characteristics ......................................................... 15

6.20

Device Individual Block Current Consumption...... 16

6.21

Worst Case Current Consumption ........................ 17

6.22

Timing Requirements, I2C Timing ......................... 17

6.23

Typical Characteristics .......................................... 19

7

Parameter Measurement Information ................ 21

8

Detailed Description ............................................ 26

8.1

Overview ................................................................. 26

8.2

Functional Block Diagram ....................................... 26

8.3

Feature Description................................................. 26

8.4

Device Functional Modes........................................ 35

8.5

Programming........................................................... 51

8.6

Register Maps ......................................................... 52

9

Application and Implementation ........................ 65

9.1

Application Information............................................ 65

9.2

Typical Applications ................................................ 65

10

Power Supply Recommendations ..................... 74

10.1

Power Rail Sequencing, Power Supply Ramp Rate,

and Mixing Supply Domains .................................... 74

10.2

Device Power-Up Timing ...................................... 75

10.3

Power Down.......................................................... 78

10.4

Power Supply Ripple Rejection (PSRR) versus

Ripple Frequency ..................................................... 78

11

Layout................................................................... 79

11.1

Layout Guidelines ................................................. 79

11.2

Reference Schematics .......................................... 81

12

Device and Documentation Support ................. 85

12.1

Documentation Support ........................................ 85

12.2

Receiving Notification of Documentation Updates 85

12.3

Community Resources.......................................... 85

12.4

Trademarks ........................................................... 85

12.5

Electrostatic Discharge Caution ............................ 85

12.6

Glossary ................................................................ 85

13

Mechanical, Packaging, and Orderable

Information ........................................................... 85

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision F (April 2014) to Revision G

Page

•

Changed Handling Ratings table to ESD Ratings .................................................................................................................. 6

•

Added Table 7 ..................................................................................................................................................................... 38

•

Added Table 10 ................................................................................................................................................................... 43

Changes from Revision E (March 2013) to Revision F

Page

•

Changed layout of data sheet to conform to new TI standards. Added the following sections: Handling Ratings,

Thermal Information, Typical Characteristics, Programming, Register Maps, Layout and Layout Guidelines ..................... 1

•

Changed from zero to one ................................................................................................................................................... 53

•

Added text at the end of the first paragraph in Power Down section .................................................................................. 78

•

Changed fOUT = 122.88 MHz, VDD Supply Noise = 100 mVpp............................................................................................ 78

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