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3D7105 Datasheet(PDF) 1 Page - Data Delay Devices, Inc.

Part No. 3D7105
Description  MONOLITHIC 5-TAP FIXED DELAY LINE (SERIES 3D7105)
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Maker  DATADELAY [Data Delay Devices, Inc.]
Homepage  http://www.datadelay.com
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3D7105 Datasheet(HTML) 1 Page - Data Delay Devices, Inc.

   
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3D7105
Doc #96006
DATA DELAY DEVICES, INC.
1
12/2/96
3 Mt. Prospect Ave. Clifton, NJ 07013
MONOLITHIC 5-TAP
FIXED DELAY LINE
(SERIES 3D7105)
FEATURES
PACKAGES
All-silicon, low-power CMOS
technology
TTL/CMOS compatible
inputs and outputs
Vapor phase, IR and wave
solderable
Auto-insertable (DIP pkg.)
Low ground bounce noise
Leading- and trailing-edge accuracy
Delay range: .75 through 80ns
Delay tolerance: 5% or 1ns
Temperature stability:
±3% typical (0C-70C)
Vdd stability:
±1% typical (4.75V-5.25V)
Minimum input pulse width: 30% of total delay
14-pin DIP and 16-pin SOIC available as drop-in
replacements for hybrid delay lines
FUNCTIONAL DESCRIPTION
The 3D7105 5-Tap Delay Line product family consists of fixed-delay
CMOS integrated circuits. Each package contains a single delay line,
tapped and buffered at 5 points spaced uniformly in time. Tap-to-tap
(incremental) delay values can range from 0.75ns through 8.0ns. The
input is reproduced at the outputs without inversion, shifted in time as per
the user-specified dash number. The 3D7105 is TTL- and CMOS-
compatible, capable of driving ten 74LS-type loads, and features both
rising- and falling-edge accuracy.
The all-CMOS 3D7105 integrated circuit has been designed as a reliable,
economic alternative to hybrid TTL fixed delay lines. It is offered in a standard 8-pin auto-insertable DIP
and a space saving surface mount 8-pin SOIC.
data
delay
devices, inc.
®
®
3
1
2
3
4
8
7
6
5
IN
O2
O4
GND
VDD
O1
O3
O5
3D7105Z
SOIC
(150 Mil)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
IN
N/C
N/C
O2
N/C
O4
N/C
GND
VDD
N/C
N/C
O1
N/C
O3
N/C
O5
3D7105S SOIC
(300 Mil)
8
7
6
5
1
2
3
4
IN
O2
O4
GND
VDD
O1
O3
O5
3D7105M DIP
3D7105H Gull-Wing
(300 Mil)
14
13
12
11
10
9
8
1
2
3
4
5
6
7
IN
N/C
N/C
O2
N/C
O4
GND
VDD
N/C
O1
N/C
O3
N/C
O5
3D7105
DIP
3D7105G Gull-Wing
3D7105K Unused pins
removed
(300 Mil)
PIN DESCRIPTIONS
IN
Delay Line Input
O1
Tap 1 Output (20%)
O2
Tap 2 Output (40%)
O3
Tap 3 Output (60%)
O4
Tap 4 Output (80%)
O5
Tap 5 Output (100%)
VCC
+5 Volts
GND Ground
N/C
No Connection
TABLE 1: PART NUMBER SPECIFICATIONS
PART NUMBER
TOLERANCES
INPUT RESTRICTIONS
DIP-8
3D7105M
3D7105H
SOIC-8
3D7105Z
DIP-14
3D7105
3D7105G
3D7105K
SOIC-16
3D7105S
TOTAL
DELAY (ns)
TAP-TAP
DELAY
(ns)
Max
Operating
Frequency
Absolute
Max
Oper. Freq.
Min
Operating
Pulse Width
Absolute
Min
Oper. P.W.
-.75
-.75
-.75
-.75
3.0
± 1.0*
0.75
± 0.4
41.7 MHz
166.7 MHz
12.0 ns
3.00 ns
-1
-1
-1
-1
4.0
± 1.0*
1.0
± 0.5
37.0 MHz
166.7 MHz
13.5 ns
3.00 ns
-1.5
-1.5
-1.5
-1.5
6.0
± 1.0*
1.5
± 0.7
30.3 MHz
166.7 MHz
16.5 ns
3.00 ns
-2
-2
-2
-2
8.0
± 1.0*
2.0
± 0.8
25.6 MHz
166.7 MHz
19.5 ns
3.00 ns
-2.5
-2.5
-2.5
-2.5
10.0
± 1.0*
2.5
± 1.0
22.2 MHz
133.3 MHz
22.5 ns
3.75 ns
-4
-4
-4
-4
16.0
± 1.0*
4.0
± 1.3
15.9 MHz
83.3 MHz
31.5 ns
6.00 ns
-5
-5
-5
-5
25.0
± 1.3
5.0
± 1.5
13.3 MHz
66.7 MHz
37.5 ns
7.50 ns
-8
-8
-8
-8
40.0
± 2.0
8.0
± 1.5
9.52 MHz
41.7 MHz
52.5 ns
12.0 ns
* Total delay referenced to Tap1 output; Input-to-Tap1 = 5.0ns
±± 1.0ns
NOTE:
Any dash number between .75 and 8 not shown is also available.
©
©1996 Data Delay Devices


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